STMicroelectronics STM32F405 Reference Manual page 1709

RM0090
Date
19-Oct-2012
Table 310. Document revision history (continued)
Version
FSMC:
Updated step b) in
transactions.
Updated Table 196: FSMC_BTRx bit
Changed Clock divide ration min in
NAND/PC Card access
Updated case of synchronous accesses in
Flash/PSRAM
Changed minimum value for ADDSET to 0 in
Table 207,
Move note from
Mode1 read
accesses to
Updated Section : WAIT management in asynchronous
Added register access in
registers and
memories and
Removed caution note in
signalss.
2
Updated Table 244: 16-bit PC Card.
(continued)
Updated step 3 in
Updated
Figure 453: Access to non 'CE don't care' NAND-Flash
note below in
Updated access to I/O Space in
Card/CompactFlash
signals and access
Section : SRAM/NOR-Flash chip-select timing registers 1..4
(FSMC_BTR1..4)). Changed bits 16 to 19 to BUSTURN in
SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4)
DEBUG:
Updated Section 38.4.3: Internal pull-up and pull-down on JTAG
pins.
Electronic signature
Updated Section 39: Device electronic signature
Updated REV_ID[15:0] to add revision Z in
device ID register (96
Updated address and example in
DocID018909 Rev 11
Changes
Section 36.3.1: Supported memories and
parameters.
controller.
Table 209, and Table 210.
Figure 435: Mode1 write accesses
accesses. Move note from
Figure 436: ModeA read
Section 36.5.6: NOR/PSRAM control
Section 36.6.2: NAND Flash / PC Card supported
transactions.
Section 36.6.1: External memory interface
Section 36.6.4: NAND Flash
Section 36.6.5: NAND Flash pre-wait
Section 36.6.7: PC
operationss. Updated
type. Updated BUSTURN bit definition in
bits).
Section 39.2: Flash
Revision history
fields.
Table 241: Programmable
Section 36.5: NOR
Table 203, Table
and Figure 434:
Figure 437: ModeA write
accesses.
accesses.
operations.
functionality.
Table 246: 16-bit PC-Card
Section :
introduction.
Section 39.1: Unique
size.
1709/1731
206,
and
1726