STMicroelectronics STM32F405 Reference Manual page 1227

RM0090
Ethernet DMA missed frame and buffer overflow counter register
(ETH_DMAMFBOCR)
Address offset: 0x1020
Reset value: 0x0000 0000
The DMA maintains two counters to track the number of missed frames during reception.
This register reports the current value of the counter. The counter is used for diagnostic
purposes. Bits [15:0] indicate missed frames due to the STM32F4xx buffer being
unavailable (no receive descriptor was available). Bits [27:17] indicate missed frames due to
Rx FIFO overflow conditions and runt frames (good frames of less than 64 bytes).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
rc_ rc_ rc_ rc_
r r r r
Bits 31:29 Reserved, must be kept at reset value.
Bit 28 OFOC: Overflow bit for FIFO overflow counter
Bits 27:17 MFA: Missed frames by the application
Indicates the number of frames missed by the application
Bit 16 OMFC: Overflow bit for missed frame counter
Bits 15:0 MFC: Missed frames by the controller
Indicates the number of frames missed by the Controller due to the host receive buffer being
unavailable. This counter is incremented each time the DMA discards an incoming frame.
Ethernet DMA receive status watchdog timer register (ETH_DMARSWTR)
Address offset: 0x1024
Reset value: 0x0000 0000
This register, when written with a non-zero value, enables the watchdog timer for the receive
status (RS, ETH_DMASR[6]).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 RSWTC: Receive status (RS) watchdog timer count
Ethernet (ETH): media access control (MAC) with DMA controller
rc_ rc_ rc_ rc_ rc_ rc_ rc_
r r r r r r
Reserved
Indicates the number of HCLK clock cycles multiplied by 256 for which the watchdog timer
is set. The watchdog timer gets triggered with the programmed value after the RxDMA
completes the transfer of a frame for which the RS status bit is not set due to the setting of
RDES1[31] in the corresponding descriptor. When the watchdog timer runs out, the RS bit
is set and the timer is stopped. The watchdog timer is reset when the RS bit is set high due
to automatic setting of RS as per RDES1[31] of any received frame.
DocID018909 Rev 11
rc_ rc_ rc_ rc_ rc_ rc_
r r r r r r r
9 8 7 6 5
MFC
rc_ rc_ rc_ rc_ rc_ rc_ rc_
r r r r r r r
9 8 7 6 5
rw rw rw rw rw rw rw rw
4 3 2 1 0
rc_ rc_ rc_ rc_ rc_
r r r r r
4 3 2 1 0
RSWTC
1227/1731
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