STMicroelectronics STM32F405 Reference Manual page 1198

Ethernet (ETH): media access control (MAC) with DMA controller
Ethernet MAC address 0 low register (ETH_MACA0LR)
Address offset: 0x0044
Reset value: 0xFFFF FFFF
The MAC address 0 low register holds the lower 32 bits of the 6-byte first MAC address of
the station.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 MACA0L: MAC address0 low [31:0]
Ethernet MAC address 1 high register (ETH_MACA1HR)
Address offset: 0x0048
Reset value: 0x0000 FFFF
The MAC address 1 high register holds the upper 16 bits of the 6-byte second MAC address
of the station.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
AE SA MBC
rw rw rw rw rw rw rw rw
Bit 31 AE: Address enable
Bit 30 SA: Source address
1198/1731
This field contains the lower 32 bits of the 6-byte MAC address0. This is used by the MAC
for filtering for received frames and for inserting the MAC address in the transmit flow control
(Pause) frames.
Reserved
When this bit is set, the address filters use the MAC address1 for perfect filtering. When this
bit is cleared, the address filters ignore the address for filtering.
When this bit is set, the MAC address1[47:0] is used for comparison with the SA fields of the
received frame.
When this bit is cleared, the MAC address1[47:0] is used for comparison with the DA fields
of the received frame.
DocID018909 Rev 11
MACA0L
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
9 8 7 6 5 4 3
9 8 7 6 5 4 3
MACA1H
RM0090
2 1 0
2 1 0