STMicroelectronics STM32F405 Reference Manual page 1097

RM0090
Bit 2 BOFF
Bit 1 EPVF: Error passive flag
Bit 0 EWGF
CAN bit timing register (CAN_BTR)
Address offset: 0x1C
Reset value: 0x0123 0000
This register can only be accessed by the software when the CAN hardware is in
initialization mode.
31 30 29
SILM LBKM
rw rw
15 14 13
Reserved
Bit 31 SILM
Bit 30 LBKM
Bits 29:26 Reserved, must be kept at reset value.
Bits 25:24 SJW[1:0]
Bit 23 Reserved, must be kept at reset value.
Bits 22:20 TS2[2:0]
:
Bus-off flag
This bit is set by hardware when it enters the bus-off state. The bus-off state is entered on
TEC overflow, greater than 255, refer to
This bit is set by hardware when the Error Passive limit has been reached (Receive Error
Counter or Transmit Error Counter>127).
:
Error warning flag
This bit is set by hardware when the warning limit has been reached
(Receive Error Counter or Transmit Error Counter≥96).
28 27 26 25
SJW[1:0]
Reserved
rw
12 11 10 9
rw
:
Silent mode (debug)
0: Normal operation
1: Silent Mode
:
Loop back mode (debug)
0: Loop Back Mode disabled
1: Loop Back Mode enabled
:
Resynchronization jump width
These bits define the maximum number of time quanta the CAN hardware is allowed to
lengthen or shorten a bit to perform the resynchronization.
t = t x (SJW[1:0] + 1)
RJW q
:
Time segment 2
These bits define the number of time quanta in Time Segment 2.
t = t x (TS2[2:0] + 1)
BS2 q
DocID018909 Rev 11
Controller area network (bxCAN)
Section 32.7.6 on page
24 23 22 21
Res. TS2[2:0]
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8 7 6 5
BRP[9:0]
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1084.
20 19 18 17
TS1[3:0]
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4 3 2 1
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16
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0
rw
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