STMicroelectronics STM32F405 Reference Manual page 1282

Advanced arm-based 32-bit mcus
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USB on-the-go full-speed (OTG_FS)
OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)
Address offset: 0x100
Reset value: 0x0200 0600
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Bits 31:16 PTXFD: Host periodic TxFIFO depth
This value is in terms of 32-bit words.
Minimum value is 16
Bits 15:0 PTXSA: Host periodic TxFIFO start address
The power-on reset value of this register is the sum of the largest Rx data FIFO depth and
largest non-periodic Tx data FIFO depth.
OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXFx)
(x = 1..3, where x is the FIFO_number)
Address offset: 0x104 + (FIFO_number – 1) × 0x04
Reset value: 0x02000400
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Bits 31:16 INEPTXFD: IN endpoint TxFIFO depth
Bits 15:0 INEPTXSA: IN endpoint FIFOx transmit RAM start address
1282/1731
PTXFSIZ
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INEPTXFD
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This value is in terms of 32-bit words.
Minimum value is 16
The power-on reset value of this register is specified as the largest IN endpoint FIFO
number depth.
This field contains the memory start address for IN endpoint transmit FIFOx. The address
must be aligned with a 32-bit memory location.
DocID018909 Rev 11
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PTXSA
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INEPTXSA
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RM0090
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