Table 2-4 Clock And Pll Signals - Motorola DSP56009 User Manual

Signal Descriptions
Clock and PLL signals
Ground Name
GND Data Bus Ground —GND
D
data bus
I/O drivers. This connection must be tied externally to all other chip
ground connections. The user must provide adequate external
decoupling capacitors.
GND Serial Interface Ground —GND
S
This connection must be tied externally to all other chip ground connections. The
user must provide adequate external decoupling capacitors.
2.4 CLOCK AND PLL SIGNALS
Note: While the PLL on this DSP is identical to the PLL described in the DSP56000
Family Manual, two of the signals have not been implemented externally.
Specifically, there is no PLOCK signal or CKOUT signal available. Therefore,
the internal clock is not directly accessible and there is no external indication
that the PLL is locked. These signals were omitted to reduce the number of
pins and allow this DSP to be put in a smaller, less expensive package.
Signal Signal
Name Type
EXTAL Input
2-6
Table 2-3 Grounds (Continued)

Table 2-4 Clock and PLL Signals

State
during
Reset
Input External Clock/Crystal —This input should be connected
to an external clock source. If the PLL is enabled, this
signal is internally connected to the on-chip PLL. The PLL
can multiply the frequency on the EXTAL pin to generate
the internal DSP clock. The PLL output is divided by two
to produce a four-phase instruction cycle clock, with the
minimum instruction time being two PLL output clock
periods. If the PLL is disabled, EXTAL is divided by two
to produce the four-phase instruction cycle clock.
DSP56009 User's Manual
Description
provides isolated ground for sections of the
D
provides isolated ground for the SHI and SAI.
S
Signal Description
MOTOROLA