Pll And Clock Oscillator; Jtag Tap And Once Module - Motorola DSP56309 User Manual

¥ SPÑstack pointer
¥ OMRÑoperating mode register
¥ SCÑstack counter register
The PCU also includes a hardware system stack (SS).
1.6.4

PLL and Clock Oscillator

The clock generator in the DSP56300 core is composed of two main blocks: the PLL,
which performs clock input division, frequency multiplication, and skew elimination;
and the clock generator (CLKGEN), which performs low-power division and clock pulse
generation.
¥ Allows change of low-power divide factor (DF) without loss of lock
¥ Output clock with skew elimination
The PLL allows the processor to operate at a high internal clock frequency using a
low-frequency clock input, a feature that offers two immediate benefits:
¥ A lower-frequency clock input reduces the overall electromagnetic interference
generated by a system.
¥ The ability to oscillate at different frequencies reduces costs by eliminating the
need to add additional oscillators to a system.
1.6.5

JTAG TAP and OnCE Module

The DSP56300 core provides a dedicated user-accessible Test Access Port (TAP) that is
fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan
Architecture. Problems associated with testing high density circuit boards have led to
development of this standard under the sponsorship of the Test Technology Committee
of IEEE and the Joint Test Action Group (JTAG). The DSP56300 core implementation
supports circuit-board test strategies based on this standard.
The test logic includes a TAP consisting of four dedicated signals, a 16-state controller,
and three test data registers. A boundary scan register links all device signals into a
single shift register. The test logic, implemented utilizing static logic design, is
independent of the device system logic. More information on the JTAG port is provided
in Section 11ÑJTAG Port
MOTOROLA
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DSP56309UM/D
DSP56309 Overview
DSP56300 Core Functional Blocks
1-11