Stop Standby Mode; Low-Power Clock Divider - Motorola DSP56600 Manual

Saving Power
Low Power Modes
A-2 Optimizing DSP56300/DSP56600 Applications
peripheral, an interrupt request is generated to take the core out of
the Wait mode.
Power consumption during a Wait Standby Mode is very low, in the
range of a few milliamperes. Please refer to the specific device data
sheet for more accurate numbers.
A.1.2

Stop Standby Mode

The Stop Standby mode is entered by using the special STOP
instruction. The STOP instruction turns off the entire chip logic until
one of the following events occur:
• Assertion of the IRQA (Interrupt Request A) pin
• Assertion of the DE (Debug Event) pin
• Transmission of a Debug Request command to the JTAG port
• Assertion of the RESET input signal
During Stop mode, the entire chip function is shut down. A
common use of the Stop mode is in systems that process data on
time intervals. When processing is complete for a specific interval,
the chip can enter Stop mode until the next time slot. This reduces
overall power consumption.
Power consumption during Stop Standby Mode is almost zero, in
the range of 10 µA. Please refer to the specific device data sheet for
more accurate numbers.
A.1.3

Low-Power Clock Divider

The on-chip clock generator includes a divider connected to the
output. This output divider can divide the operating frequency
without causing the PLL to lose lock. Thus, it can be easily used to
reduce the chip's power consumption during time intervals in
which the application does not require the full MIPS capability of
DSP device.
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