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1.6.2.2
Offset Register File (N0-N3)
The Offset Register File consists of four, sixteen-bit registers. The file contains the offset
registers N0-N3 and usually contains offset values used to update address pointers. Each
offset register may be read or written by the Global Data Bus. Each offset register is used
as an input to the modulo arithmetic unit when the same number address register is read
and used as an input to the modulo arithmetic unit.
1.6.2.3
Modifier Register File (M0-M3)
The Modifier Register File consists of four, 16-bit registers. The file contains the modifier
registers M0-M3 and usually specifies the type of arithmetic used to modify an address
register during address register update calculations — linear, modulo or reverse carry.
Each modifier register may be used as an input to the modulo arithmetic unit or written by
the Global Data Bus. Each modifier register is read when the same number address reg-
ister is read and used as an input to the modulo arithmetic unit. Each modifier register is
preset to $FFFF during a processor reset. Note that when R3 is used for the second read,
only linear arithmetic is available on this address register.
1.6.3
Program Control Unit
The program control unit features loop address and loop counter registers which are ded-
icated to supporting the hardware DO loop instruction in addition to the standard program
flow control resources such as a program counter, status register, and system stack. With
the exception of the program counter, all registers are read/write to facilitate system debug.
1.6.3.1
Program Counter (PC)
This 16-bit register contains the address of the next location to be fetched from program
memory space. The PC may point to instructions, data operands, or addresses of oper-
ands. References to this register are always inherent and are implied by most instructions.
This special purpose address register is stacked when program looping is initiated, when
a branch or a jump to subroutine is performed, and when interrupts occur (except for fast
interrupts).
1.6.3.2
Status Register (SR)
The SR is a 16-bit register consisting of an 8-bit Mode Register (MR) and an 8-bit Condi-
tion Code Register (CCR) — see Figure 1-11. The MR register is the high-order 8 bits of
the SR; the CCR register is the low-order 8 bits.
The MR bits are only affected by processor reset, exception processing, the DO, ENDDO,
RTI, and SWI instructions and by instructions which directly reference the MR register
(e.g., MOVE, ANDI, ORI). During processor reset, the interrupt mask bits of the mode reg-
ister will be set, the scaling mode bits, loop flag, and the forever flag will be cleared. The
CCR is a special purpose control register which defines the current user state of the pro-
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PROGRAMMING MODEL
DSP56156 OVERVIEW
MOTOROLA
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