Figure 6-3 Host Status Register (Hsr) (X:$Ffffc3) - Motorola DSP56309 User Manual

6.5.4 Host Status Register (HSR)
The HSR is a 16-bit, read-only status register by which the DSP reads the HI08 status and
flags. The host processor cannot access it directly. Reserved bits are read as 0 and should
be written with 0. The initialization values for the HSR bits are described in
Section 6.5.9ÑDSP Side Registers After Reset on page 6-18.
15 14 13
ÑReserved bit, read as 0, should be written with 0 for future compatibility.

Figure 6-3 Host Status Register (HSR) (X:$FFFFC3)

6.5.4.1 HSR Host Receive Data Full (HRDF) Bit 0
The HRDF bit indicates that the host receive data register (HRX) contains data from the
host processor. HRDF is set when data is transferred from the TXH:TXM:TXL registers
to the HRX register. If HRDF is set, the HI08 generates a receive data full DMA request.
HRDF is cleared when the DSP core reads the HRX. HRDF is also cleared when the host
processor uses the initialize function.
6.5.4.2 HSR Host Transmit Data Empty (HTDE) Bit 1
The HTDE bit indicates that the host transmit data register (HTX) is empty and can be
written by the DSP core. HTDE is set when the HTX register is transferred to the
RXH:RXM:RXL registers. HTDE is also set when the host processor uses the initialize
function. If HTDE is set, the HI08 generates a transmit data full DMA request. HTDE is
cleared when HTX is written by the DSP core.
6.5.4.3 HSR Host Command Pending (HCP) Bit 2
The HCP bit indicates that the host has set the HC bit and that a host command interrupt
is pending. The HCP bit reflects the status of the HC bit in the CVR. HC and HCP are
cleared by the HI08 hardware when the interrupt request is serviced by the DSP core. If
the host clears HC, HCP is also cleared.
6.5.4.4 HSR Host Flags 0, 1 (HF[1:0]) Bits 3, 4
HF[1:0] bits are used as general-purpose flags for host-to-DSP communication. HF[1:0]
can be set or cleared by the host. These bits reflect the status of host flags HF[1:0] in the
ICR on the host side. They can be used individually or as encoded pairs in a simple
host-to-DSP communication protocol implemented in both the DSP and the host
processor software.
6.5.4.5 HSR Reserved Bits 5-15
These bits are reserved. They are read as 0 and should be written with 0.
MOTOROLA
12 11 10 9
DSP56309UM/D
HI08 DSP Side ProgrammerÕs Model
8 7 6 5
Host Interface (HI08)
4 3 2 1
HF1 HF0 HCP HTDE HRDF
0
AA0659
6-11