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When HFM1 = 1 and HFM0 = 1, the wide-spike-tolerance filter mode is selected. In
this mode the filters eliminate spikes up to 100 ns. This mode is recommended for use
in noisy environments; the bit-rate transfer is strictly limited. The wide-spike-
tolerance filter mode is highly recommended for use in I
2
conforms to the I
C bus specification and improves noise immunity.
Note: HFM[1:0] are cleared during hardware reset and software reset.
After changing the filter bits in the HCKR to a non-bypass mode (HFM[1:0] not equal
to '00'), the programmer should wait at least ten times the tolerable spike width
before enabling the SHI (setting the HEN bit in the HCSR). Similarly, after changing
2
the I
C bit in the HCSR or the CPOL bit in the HCKR, while the filter mode bits are in
the non-bypass mode (HFM[1:0] not equal to '00'), the programmer should wait at
least ten times the tolerable spike width before enabling the SHI (setting HEN in the
HCSR).
5.3.6
SHI Control/Status Register (HCSR)—DSP Side
The HCSR is a 24-bit read/write register that controls the SHI operation and reflects
its status. Each bit is described in one of the following paragraphs. When in the Stop
state or during individual reset, the HCSR status bits are reset to their hardware-reset
state, while the control bits are not affected.
5.3.6.1
HCSR Host Enable (HEN)—Bit 0
The read/write control bit Host Enable (HEN) enables the overall operation of the
SHI. When HEN is set, SHI operation is enabled. When HEN is cleared, the SHI is
disabled (individual reset state, see below). The HCKR and the HCSR control bits are
not affected when HEN is cleared. When operating in Master mode, HEN should be
cleared only after the SHI is idle (HBUSY = 0). HEN is cleared during hardware reset
and software reset.
5.3.6.1.1
SHI Individual Reset
While the SHI is in the individual reset state, SHI input pins are inhibited, output and
bidirectional pins are disabled (high impedance), the HCSR status bits and the
transmit/receive paths are reset to the same state produced by hardware reset or
software reset. The individual reset state is entered following a one-instruction-cycle
delay after clearing HEN.
5.3.6.2
HCSR I
The read/write control bit HI
2
modes. When HI
C is cleared, the SHI operates in the SPI mode. When HI
the SHI operates in the I
MOTOROLA
2
C/SPI Selection (HI
2
C selects whether the SHI operates in the I
2
2
C mode. HI
C affects the functionality of the SHI pins as
DSP56009 User's Manual
Serial Host Interface Programming Model
2
C bus systems as it fully
2
C)—Bit 1
Serial Host Interface
2
C or SPI
2
C is set,
5-13
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