What Are The Program Flow-Control Pipeline Interlocks; Move To The Status Register (Sr); Move To The System Stack High/Low (Ssh/Ssl) - Motorola DSP56600 Manual

Pipeline Interlocks
Program Flow-Control Pipeline Interlocks
6-10 Optimizing DSP56300/DSP56600 Applications
6.4.1 What are the Program Flow-Control Pipeline
Interlocks?
Some of the flow-control interlocks may exist only in very unique
sequences and will not be described in this paragraph. The
interlocks that are not described here are:
• Write to or Read from a Control Register inside a do-loop
• Write to the Stack Pointer (SP) or Stack Counter (SC)
• Write to the Loop Address (LA) register after a write to the
Status Register (SR)
• A DO Loop with only one instruction in the loop.
• A nulled REP or DO loops.
The above sequences are described in detail in the Family Manual.
For the other cases, the following legend is used:
• I1—An address of an instruction, where I2, I3, I4 are used to
indicate the next instructions in the program flow
• MOVE—any type of MOVE, MOVEM, MOVEP, MOVEC,
BSET, BCHG, BCLR,BTST
• JMP—any type of JMP, Jcc, BRA, Bcc, JSR, JScc, BSR, BScc,
JSET, JCLR, JSSET, JSCLR, BRSET, BRCLR, BSSET, BSCLR.
• (LA)—the last address of a DO LOOP
• (LA-i)—the address of an instruction word located at LA-i
• CR—Control Register, every one of the registers LA, LC, SR,
SP, SC, SSH, SSL, OMR
6.4.1.1

MOVE to the Status Register (SR)

Whenever I1 is a MOVE to SR, then I2 will be delayed by 1 clock
cycle.
6.4.1.2

MOVE to the System Stack High/Low (SSH/SSL)

Whenever I1 is a MOVE to SSH or to SSL, and I3 is any one of the
instructions DO, DOR, RTI, RTS, ENDDO or BRKcc, then I3 will be
delayed by 3 clock cycles.
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