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Reset, Configuration, and EOnCE Event Signals
1.4 Reset, Configuration, and EOnCE Event Signals
Signal Name
DBREQ
EE0
HPE
EE1
EE2
EE3
1-6
Table 1-3. Reset, Configuration, and EOnCE Event Signals
Type
Input
Debug Request
Determines whether to go into SC140 Debug mode when PORESET is deasserted.
1
Enhanced OnCE (EOnCE) Event 0
After PORESET is deasserted, you can configure EE0 as an input (default) or an output.
Input
Debug request, enable Address Event Detection Channel 0, or generate one of the
EOnCE events.
Output
Detection by Address Event Detection Channel 0. Used to trigger external debugging
equipment.
Input
Host Port Enable
When this pin is asserted during PORESET, the Host port is enabled, the system data bus
is 32 bits wide, and the Host must program the reset configuration word.
1
EOnCE Event 1
After PORESET is deasserted, you can configure EE1 as an input (default) or an output.
Input
Enable Address Event Detection Channel 1 or generate one of the EOnCE events.
Output
Debug Acknowledge or detection by Address Event Detection Channel 1. Used to trigger
external debugging equipment.
1
EOnCE Event 2
After PORESET is deasserted, you can configure EE2 as an input (default) or an output.
Input
Enable Address Event Detection Channel 2 or generate one of the EOnCE events or
enable the Event Counter.
Output
Detection by Address Event Detection Channel 2. Used to trigger external debugging
equipment.
1
EOnCE Event 3
After PORESET is deasserted, you can configure EE3 as an input (default) or an output.
See the Emulation and Debug chapter in the SC140 DSP Core Reference Manual for
details on the ERCV Register.
Input
Enable Address Event Detection Channel 3 or generate one of the EOnCE events.
Output
EOnCE Receive Register (ERCV) was read by the DSP. Used to trigger external
debugging equipment.
Signal Description
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