Motorola DSP56000 Manual: Address Generation Unit And Addressing Modes; Agu Architecture

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ADDRESS GENERATION UNIT AND ADDRESSING MODES

4.1
ADDRESS GENERATION UNIT AND ADDRESSING MODES
This section contains three major subsections. The first subsection describes the hard-
ware architecture of the address generation unit (AGU), the second subsection
describes the programming model, and the third subsection describes the addressing
modes, explaining how the Rn, Nn, and Mn registers work together to form a memory
address.
4.2
AGU ARCHITECTURE
The AGU is shown in the DSP56K block diagram in Figure 4-1. It uses integer arithmetic
to perform the effective address calculations necessary to address data operands in
memory, and contains the registers used to generate the addresses. It implements lin-
ear, modulo, and reverse-carry arithmetic, and operates in parallel with other chip
resources to minimize address-generation overhead.
The AGU is divided into two identical halves, each of which has an address arithmetic
logic unit (ALU) and four sets of three registers (see Figure 4-2). They are the address
registers (R0 - R3 and R4 - R7), offset registers (N0 - N3 and N4 - N7), and the modifier
registers (M0 - M3 and M4 - M7). The eight Rn, Nn, and Mn registers are treated as reg-
ister triplets — e.g., only N2 and M2 can be used to update R2. The eight triplets are
R0:N0:M0, R1:N1:M1, R2:N2:M2, R3:N3:M3, R4:N4:M4, R5:N5:M5, R6:N6:M6, and
R7:N7:M7.
The two arithmetic units can generate two 16-bit addresses every instruction cycle — one
for any two of the XAB, YAB, or PAB. The AGU can directly address 65,536 locations on
the XAB, 65,536 locations on the YAB, and 65,536 locations on the PAB. The two inde-
pendent address ALUs work with the two data memories to feed the data ALU two
operands in a single cycle. Each operand may be addressed by an Rn, Nn, and Mn triplet.
4.2.1
Address Register Files (Rn)
Each of the two address register files (see Figure 4-2) consists of four 16-bit registers. The
two files contain address registers R0 - R3 and R4 - R7, which usually contain addresses
used as pointers to memory. Each register may be read or written by the global data bus
(GDB). When read by the GDB, 16-bit registers are written into the two least significant
bytes of the GBD, and the most significant byte is set to zero. When written from the GBD,
only the two least significant bytes are written, and the most significant byte is truncated.
Each address register can be used as input to its associated address ALU for a register
update calculation. Each register can also be written by the output of its respective ad-
dress ALU. One Rn register from the low address ALU and one Rn register from the high
address ALU can be accessed in a single instruction.
MOTOROLA
ADDRESS GENERATION UNIT
4 - 3

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