Figure 3-5 Operating Mode Register (Omr) - Motorola DSP56009 User Manual

Table 3-2 Internal I/O Memory Map (Continued)
Location
:
X: $FFC0
3.4 OPERATING MODE REGISTER (OMR)
The Operating Mode Register (OMR) is illustrated in Figure 3-5.
23
Bits 5 and 7–23 are reserved, read as 0s, and should be written with 0s
for future compatibility.
3.4.1 DSP Operating Mode (MC, MB, MA)—Bits 4, 1, and 0
The DSP operating mode bits, MC, MB, and MA, select the operating mode of the
DSP56009. These operating modes are described in Section 3.5 Operating Modes
on the following page. On hardware reset, MC, MB, and MA are loaded from the
external mode select pins MODC, MODB, and MODA, respectively. After the DSP
leaves the reset state, MC, MB, and MA can be changed under software control.
3.4.2 Program RAM Enable A (PEA)—Bit 2
The Program RAM Enable A (PEA) bit is used to map 768 words of the internal X
data memory into internal Program RAM. When PEA is set, 768 words of X data
RAM (locations $0C00–$0EFF) are mapped into the program memory space
(locations $0800–$0AFF). The internal memory maps, as controlled by the PEA bit,
MOTOROLA
Register
:
Reserved
7 6 5
SD MC

Figure 3-5 Operating Mode Register (OMR)

DSP56009 User's Manual
Memory, Operating Modes, and Interrupts
Operating Mode Register (OMR)
4 3 2 1
PEB PEA MB
0
MA
Operating Mode A,B
Program RAM Enable A
Program RAM Enable B
Operating Mode C
Stop Delay
AA0291k
3-11