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USB GPIF Registers
to buf_wstart_row of the user image buffer. The buffer write state machine accepts buf_wstart_numrows of data, after which the buffer
stops writing data until a new write to this register is performed. In addition, writing to this register resets the USB / GPIF FIFO.
(2)
Valid values for buf_wstart_row are 0 through (TOTAL_ROWS_ON_DMD – 1). Buf_wstart_row must be less than or equal to
TOTAL_ROWS_ON_DMD – buf_wstart_numrows.
(3)
Buf_wstart_numrows valid values are 1 thru TOTAL_ROWS_ON_DMD.
5.1.8 USB GPIF FIFO Read Burst Size (0x0028) - [Obsolete]
Address
BITS
0x0028
(31:10)
(9:0)
(1)
This register is no longer used by the apps FPGA logic. The USB GPIF logic still supports reads/writes for this register, but the
contents are not currently used.
5.1.9 User Row Command Register (0x002C)
Address
BITS
0x002C
(31:29)
28
27
(26:16)
15
(14:4)
(3:2)
(1:0)
(1)
When F1S is '1' (F1S = force ones), all 1's data is sent to the DLPC910 for the given row cycles.
(2)
ROWMD has the following effect on user image buffer reads:
•
"00" – no action.
•
"01" – increments buffer read address counter then sends addressed buffer row data to DMD. Continues this until numrows (bits
26:16) have been sent.
•
"10" – loads apps DLP ROWAD counter with ROWAD. Sends ROWAD to DLPC910. Loads buffer read address counter with
ROWAD. Sends addressed buffer row to DLPC910.
•
"11" – Sends ROWAD = zeros to DLPC910. Clears buffer read address counter to zeros. Sends buffer row 0 data to DLPC910.
(3)
The User Row Command register is used to move data from the user image buffer to the DMD. When the register is written, ROWMD
and ROWAD are forwarded to the DLPC910 controller along with data read from the user image buffer. Additional details on the
function of these row control signals can be found in the DLPC910 data sheet.
Apps FPGA continuously sends no-op row commands to the DLPC910 controller when the controller is not
responding to writes to this register.
5.1.10 User Block Command Register (0x0030)
Address
BITS
0x0030
(31:9)
8
(7:4)
(3:2)
(1:0)
(1)
Writing to the user block command register instructs apps FPGA to forward the block command in this register to the DLPC910
controller. Block command details are described in the DLPC910 data sheet. Forwarded block commands include the appropriate
synchronization with DCLK and DVALID.
®
26
DLP
DLPC910 Apps FPGA Guide
Description
Not used
(1)
FIFO read burst size - obsolete
Description
Not used
(1)
F1S
Not used
(2) (3)
Numrows
Not used
(2) (3)
ROWAD
Not used
(2) (3)
ROWMD
Description
Not used
(1)
RST2BLKZ
(1)
BLKAD
Not used
(1)
BLKMD
Copyright © 2023 Texas Instruments Incorporated
Default
R/W
zeros
R/W
N/A
R/W
Default
R/W
zeros
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0x000
R/W
"00"
R/W
"00"
R/W
Default
R/W
zeros
R/W
1
R/W
0x0
R/W
zeros
R/W
"00"
R/W
DLPU125 – JUNE 2023
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