Transfer Complete Code (Tcc) To Dma Interrupt Mapping - Texas Instruments TMS320C6201 Reference Manual

Table 6–9. Transfer Complete Code (TCC) to DMA Interrupt Mapping
The TCC field can have values between 0000b to 1111b. These are directly
mapped to the CIPR bits as shown in Table 6–9. For example, if TCC = 1100b,
CIPR[12] is set to 1 after the transfer is complete, and this generates a CPU
interrupt only if CIER[12] = 1. The user can program the TCC value to be any-
thing between 0000b to 1111b for any EDMA channel. In other words, there
need not necessarily be a direct relation between the channel number and the
TCC value. This allows multiple channels having the same TCC value to cause
the CPU to execute the same ISR (for different channels).
TCC in Options CIPR[15:0] Bits
(TCINT=1)
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
EDMA Interrupt Generation
Set
CIPR[0]
CIPR[1]
CIPR[2]
CIPR[3]
CIPR[4]
CIPR[5]
CIPR[6]
CIPR[7]
CIPR[8]
CIPR[9]
CIPR[10]
CIPR[11]
CIPR[12]
CIPR[13]
CIPR[14]
CIPR[15]
EDMA Controller 6-33