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TMS320C6201
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
functional and CPU (DSP core) block diagram
SDRAM
SBSRAM
32
SRAM
ROM/FLASH
I/O Devices
Framing Chips:
H.100, MVIP,
SCSA, T1, E1
AC97 Devices,
SPI Devices,
Codecs
Synchronous
FIFOs
32
I/O Devices
HOST CONNECTION
Master /Slave
TI PCI2040
Power PC
683xx
960
4
Access/Cache
External Memory
Interface (EMIF)
Timer 0
Timer 1
Multichannel
Buffered Serial
Port 0
Multichannel
Buffered Serial
Port 1
Peripheral Control Bus
Interrupt
Selector
Direct Memory
Access Controller
(DMA)
Host Port
(4 Channels)
Interface
(HPI)
PLL
(x1, x4)
POST OFFICE BOX 1443
C6201 Digital Signal Processors
Program
Internal Program Memory
Controller
C62x CPU (DSP Core)
Instruction Fetch
Instruction Dispatch
Instruction Decode
Data Path A
Data Path B
A Register File
B Register File
.L1 .S1 .M1 .D1
.D2 .M2
Data
Access
Controller
Power-
Down
Logic
Boot Configuration
•
HOUSTON, TEXAS 77251--1443
(64K Bytes)
Control
Registers
Control
Logic
Test
In-Circuit
Emulation
Interrupt
.S2
.L2
Control
Internal Data
Memory
(64K Bytes)
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