Hpi Input Control Signals Function Selection Descriptions; Hpi Data Write Access - Texas Instruments TMS320C6201 Reference Manual

HPI Signal Descriptions
Table 7–2. HPI Input Control Signals Function Selection Descriptions
7.2.3 Halfword Identification Select: HHWIL
7-8
HCNTL1 HCNTL0
0 0
0 1
1 0
1 1
HHWIL identifies the first or second halfword of a transfer, but not the most sig-
nificant or least significant halfword. The status of the HWOB bit of the HPIC
register, described later in this chapter, determines which halfword is least sig-
nificant or most significant. HHWIL is low for the first halfword and high for the
second halfword.
Since byte enable pins are removed from the 'C6211/C6711 HPI, HHWIL in
combination with HWOB specify the half-word position in the data register,
HPID. This is shown in Table 7–3 along with the LSB address bits depending
on endianness.
Table 7–3. HPI Data Write Access
Data-Type
Little-Endian (LE)/
Big-Endian (BE)
Half-word:
Little endian (LE)
Big endian (BE)
Half-word:
Little endian (LE)
Big endian (BE)
Word:
Little endian (LE)
Big endian (BE)
Word:
Little endian (LE)
Big endian (BE)
Description
Host reads from or writes to the HPI control register (HPIC).
Host reads from or writes to the HPI address register (HPIA).
Host reads or writes to the HPI data register (HPID). The HPI
address register (HPIA) is postincremented by a word ad-
dress (four byte addresses).
Host reads or writes to the HPI data register (HPID). HPI ad-
dress register (HPIA) is not affected.
First Write
(HHWIL=0) /
Logical LSB
HWOB
Address Bits
0 MS half-word
LE = 10
BE = 00
1 LS half-word
LE = 00
BE = 10
0 MS half-word
LE = 00
BE = 00
1 LS half-word
LE = 00
BE = 00
Second Write
(HHWIL=1) /
Logical LSB
Address Bits
LS half-word
LE = 00
BE = 10
MS half-word
LE = 10
BE = 00
LS half-word
LE = 00
BE = 00
MS half-word
LE = 00
BE = 00