Apb Clock Control Register 0 - Apbccr0 - Holtek HT32F52243 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52243/HT32F52253
APB Clock Control Register 0 – APBCCR0
This register specifies the APB peripherals clock enable bits.
Offset: 0x02C
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
EXTIEN
Type/Reset RW 0 RW
7
Reserved
Type/Reset
Bits Field
[15] EXTIEN
[14] AFIOEN
[13] UR3EN
[12] UR2EN
[11] UR1EN
[10] UR0EN
[9] USR1EN
Rev. 1.20
30 29 28
22 21 20
14 13 12
AFIOEN UR3EN UR2EN
0 RW 0 RW
6 5
SPI1EN SPI0EN
RW 0 RW
Descriptions
External Interrupt Clock Enable
0: EXTI clock is disabled
1: EXTI clock is enabled
Set and reset by software.
Alternate Function I/O Clock Enable
0: AFIO clock is disabled
1: AFIO clock is enabled
Set and reset by software.
UART3 Clock Enable
0: UART3 clock is disabled
1: UART3 clock is enabled
Set and reset by software.
UART2 Clock Enable
0: UART2 clock is disabled
1: UART2 clock is enabled
Set and reset by software.
UART1 Clock Enable
0: UART1 clock is disabled
1: UART1 clock is enabled
Set and reset by software.
UART0 Clock Enable
0: UART0 clock is disabled
1: UART0 clock is enabled
Set and reset by software.
USART1 Clock Enable
0: USART1 clock is disabled
1: USART1 clock is enabled
Set and reset by software.
91 of 501
27 26
Reserved
19 18
Reserved
11 10
UR1EN UR0EN
0 RW 0 RW
4 3 2
Reserved I2C2EN
0 RW
25 24
17 16
9 8
USR1EN USR0EN
0 RW 0 RW 0
1 0
I2C1EN I2C0EN
0 RW 0 RW 0
September 19, 2018