Apb Clock Control Register 0 - Apbccr0 - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230
APB Clock Control Register 0 – APBCCR0
This register specifies the APB peripherals clock enable control bits.
Offset: 0x02C
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
EXTIEN
Type/Reset RW 0 RW
7
Reserved
Type/Reset
Bits Field
[15] EXTIEN
[14] AFIOEN
[10] UREN
[8] USREN
[4] SPIEN
[0] I2CEN
Rev. 1.10
30 29 28
22 21 20
14 13 12
AFIOEN Reserved
0
6 5
SPIEN
RW
Descriptions
External Interrupt Clock Enable
0: EXTI clock is disabled
1: EXTI clock is enabled
Set and reset by software.
Alternate Function I/O Clock Enable
0: AFIO clock is disabled
1: AFIO clock is enabled
Set and reset by software.
UART Clock Enable
0: UART clock is disabled
1: UART clock is enabled
Set and reset by software.
USART Clock Enable
0: USART clock is disabled
1: USART clock is enabled
Set and reset by software.
SPI Clock Enable
0: SPI clock is disabled
1: SPI clock is enabled
Set and reset by software.
I 2 C Clock Enable
0: I 2 C clock is disabled
1: I 2 C clock is enabled
Set and reset by software.
88 of 366
27 26
Reserved
19 18
Reserved
11 10
UREN
RW
4 3 2
Reserved
0
25 24
17 16
9 8
Reserved USREN
0 RW 0
1 0
I2CEN
RW 0
November 09, 2018