Register Descriptions; Flash Target Address Register - Tadr - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230

Register Descriptions

Flash Target Address Register – TADR
This register specifies the target address of the page erase and word programming operations.
Offset: 0x000
Reset value: 0x0000_0000
31
Type/Reset RW 0 RW
23
Type/Reset RW 0 RW
15
Type/Reset RW 0 RW
7
Type/Reset RW 0 RW
Bits Field
[31:0] TADB
Rev. 1.10
30 29 28
0 RW 0 RW
22 21 20
0 RW 0 RW
14 13 12
0 RW 0 RW
6 5
0 RW 0 RW
Descriptions
Flash Target Address Bits
For programming operations, the TADR register specifies the address where the
data is written. Since the programming length is 32-bit, the TADR should be set as
word-aligned (4 bytes). The TADB [1:0] bits will be ignored during programming
operations. For page erase operations, the TADR register contains the page address
which is going to be erased. Since the page size is 1 KB, the TADB [9:0] bits will
be ignored in order to limit the target address as 1 Kbyte-aligned. For 32 KB main
Flash addressing, the TADB [31:16] bits should be zero while the TADB [31:15] bits
should be zero for 16 KB main Flash addressing. The region of which the address
ranges from 0x1FF0_0000 to 0x1FF0_03FF is the 1KB Option Byte. This field for the
available Flash address must be under 0x1FFF_FFFF. Otherwise, the Invalid Target
Address interrupt will occur if the corresponding interrupt enable bit is set.
41 of 366
27 26
TADB
0 RW 0 RW
19 18
TADB
0 RW 0 RW
11 10
TADB
0 RW 0 RW
4 3 2
TADB
0 RW 0 RW
25 24
0 RW 0 RW 0
17 16
0 RW 0 RW 0
9 8
0 RW 0 RW 0
1 0
0 RW 0 RW 0
November 09, 2018