Features; Functional Descriptions; Vdd Power Domain - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230

Features

▄
Two power domains: V
▄
Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down modes.
▄
Internal Voltage regulator supplies 1.5 V voltage source.
▄
Additional Depletion MOS supplies 1.5 V voltage source with low leakage and low operating
current.
▄
A power reset is generated when one of the following events occurs:
● Power-on / Power-down reset (POR / PDR reset).
● When exiting Power-Down mode.
● The control bits BODEN = 1, BODRIS=0 and the supply power V
▄
BOD Brown Out Detector can issue a system reset or an interrupt when V
lower than the Brown Out Detector voltage V
▄
LVD Low Voltage Detector can issue an interrupt or wakeup event when V
programmable threshold voltage V

Functional Descriptions

V Power Domain
DD
LDO Power Control
The LDO will be automatically switched off when one of the following conditions occurs:
▄
The Power-Down or Deep-Sleep 2 mode is entered.
▄
The control bits BODEN = 1, BODRIS = 0 and the supply power V
▄
The supply power V
The LDO will be automatically switched on by hardware when the supply power V
of the following conditions occurs:
▄
Resume operation from the power saving mode – LVD wakeup and WAKEUP pin rising edge.
▄
Detect a falling edge on the external reset pin (nRST).
▄
The control bit BODEN = 1 and the supply power V
To enter the Deep-Sleep1 mode, the PWRCU will request the LDO to operate in a low current
mode, LCM. To enter the Deep-Sleep 2 mode, the PWRCU will turn off the LDO and turn on the
DMOS to supply an alternative 1.5 V power.
Voltage Regulator
The voltage regulator, LDO, Depletion MOS, DMOS, Low voltage Detector, LVD, High Speed
Internal oscillator, HSI, and Low Speed Internal RC oscillator, LSI, are operated under the V
power domain. The LDO can be configured to operate in either normal mode (LDOOFF = 0,
LDOLCM = 0, I
= Low current mode) to supply the 1.5 V power. An alternative 1.5 V power source is the output
of the DMOS which has low static and driving current characteristics. It is controlled using the
DMOSON bit in the PWRCR register. The DMOS output has weak output current and regulation
capability and only operate in the Deep-Sleep 2 mode for data retention purposes in the V
power domain.
Rev. 1.10
3.3 V and V
DD DD15
.
LVD
≤ V
DD PDR
= High current mode) or low current mode (LDOOFF = 0, LDOLCM =1, I
OUT
58 of 366
1.5 V power domains.
DD
.
BOD
≤ V
DD
> V .
DD BOD
≤ V .
BOD
power source is
DD
is lower than a
DD
.
BOD
> V if any
DD POR
DD
OUT
DD15
November 09, 2018