Vdd Power Domain - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345
Backup Registers and Isolation Cells
Ten 32-bit registers, up to 40 bytes, are located in the Backup Domain for user application data
storage. These registers are powered by V
core power is switched off. The Backup Registers are only reset by the Backup Domain power-on-
reset, PORB, or the Backup Domain software reset, BAKRST. When the device resumes operation
from the 1.5 V power, either by Hardware or Software, access to the Backup registers and the RTC
registers are disabled by the isolation cells which protect these registers against possible parasitic
write accesses. To resume access operations, users must disable these isolation cells by setting the
BKISO bit to 1 in the LPCR register of the Clock Control Unit.
LDO Power Control
The LDO will be automatically switched off when one of the following conditions occurs:
▄
The Power-Down or Deep-Sleep 2 mode is entered.
▄
The control bits BODEN = 1, BODRIS = 0 and the supply power V
▄
The supply power V
The LDO will be automatically switched on by hardware when the supply power V
of the following conditions occurs:
▄
Resume operation from the power saving mode – RTC wakeup, LVD wakeup and WAKEUP pin
rising edge.
▄
Detect a falling edge on the external reset pin (nRST).
▄
The control bit BODEN = 1 and the supply power V
To enter the Deep-Sleep1 mode, the PWRCU will request the LDO to operate in a low current
mode, LCM. To enter the Deep-Sleep 2 mode, the PWRCU will turn off the LDO and turn on the
DMOS to supply an alternative 1.5 V power.
V Power Domain
DD
Voltage Regulator
The voltage regulator, LDO, Depletion MOS, DMOS, Low voltage Detector, LVD and High Speed
Internal oscillator, HSI are operated under the V
operate in either normal mode (LDOOFF = 0, SLEEPDEEP = 0, I
current mode (LDOOFF = 0, SLEEPDEEP=1, I
An alternative 1.5 V power source is the output of the DMOS which has low static and driving
current characteristics. It is controlled using the DMOSON bit in the BAKCR register. The DMOS
output has weak output current and regulation capability and only operates in the Deep-Sleep 2
mode for data retention purposes in the V
Power On Reset (POR) / Power Down Reset (PDR)
The device has an integrated POR / PDR circuitry that allows proper operation starting from/down
to 2.0 V. The device remains in Power-Down mode when V
without the need for an external reset circuit. For more details of the power on / power down reset
threshold voltage, refer to the electrical characteristics of the corresponding datasheet.
Rev. 1.10
which constantly supplies power when the 1.5 V
BAK
≤ V
DD PDR
DD
= Low current mode) to supply the 1.5 V power.
OUT
power domain.
DD15
71 of 590
≤ V .
DD BOD
> V .
DD BOD
power domain. The LDO can be configured to
= High current mode) or low
OUT
is below a specified threshold V
DD
November 28, 2018
> V if any
DD POR
,
PDR