Interrupts And Status; Pdma Interface; Register Map; Table 55. Usart Register Map - Holtek HT32F12345 User Manual

32-Bit Arm ® Cortex ® -M3 MCU
HT32F12345

Interrupts and Status

The USART can generate interrupts when the following event occurs and corresponding interrupt
enable bits are set:
▄
Receive FIFO time-out interrupt: An interrupt will be generated when the USART receive FIFO
does not receive a new data package during the specified time-out interval.
▄
Receiver line status interrupts: The interrupts will be generated when the USART receiver overrun
error, parity error, framing error, or break events occurred.
▄
Transmit FIFO threshold level interrupt: An interrupt will be generated when the data to be transmitted
in the USART Transmit FIFO is less than the specified threshold level.
▄
Transmit complete interrupt: An interrupt will be generated when the Transmit FIFO is empty
and the content of the transmit shift register (TSR) is also completely shifted.
▄
Receive FIFO threshold level interrupt: An interrupt will be generated when the FIFO received
data amount has reached the specified threshold level.

PDMA Interface

The PDMA interface is integrated in the USART. The PDMA function can be enabled by setting
the TXDMAEN or RXDMAEN bit in the USRCR register to 1 in the transmit or receive mode
respectively. When the data to be transmitted in the USART Transmit FIFO is less than the TX
FIFO threshold level specified by the TXTL field in the USRFCR register and the TXDMAEN
bit is set to 1, the PDMA function will be activated to move data from a source location into the
USART TX FIFO.
Similarly, when the received data amount in the receive FIFO is equal to the RX FIFO threshold
level specified by the RXTL field in the USRFCR register and the RXDMAEN bit is set to 1, the
PDMA function will be activated to move data from the USART RX FIFO to a specific destination
location. For a mode detailed description on the PDMA configurations, refer to the PDMA chapter.

Register Map

The following table shows the USART registers and reset values.

Table 55. USART Register Map

Register
USART0 Base Address = 0x4000_0000
USART1 Base Address = 0x4004_0000
USRDR
USRCR
USRFCR
USRIER
USRSIFR
USRTPR
IrDACR
RS485CR
SYNCR
USRDLR
USRTSTR
Rev. 1.10
Offset
0x000 USART Data Register
0x004 USART Control Register
0x008 USART FIFO Control Register
0x00C USART Interrupt Enable Register
0x010 USART Status & Interrupt Flag Register
0x014 USART Timing Parameter Register
0x018 USART IrDA Control Register
0x01C USART RS485 Control Register
0x020 USART Synchronous Control Register
0x024 USART Divider Latch Register
0x028 USART Test Register
441 of 590
Description Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0180
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0010
0x0000_0000
November 28, 2018