Interrupts And Status; Register Map; Table 48. Usart Register Map - Holtek HT32F52220 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52220/HT32F52230

Interrupts and Status

The UART can generate interrupts when the following event occurs and corresponding interrupt
enable bits are set:
▄
Receive FIFO time-out interrupt: An interrupt will be generated when the USART receive FIFO
does not receive a new data packet during the specified time-out interval.
▄
Receiver line status interrupts: The interrupt will be generated when the USART receiver overrun
error, parity error, framing error or break events occurs.
▄
Transmit FIFO threshold level interrupt: An interrupt will be generated when the data to be
transmitted in the USART Transmit FIFO is less than the specified threshold level.
▄
Transmit complete interrupt: An interrupt will be generated when the Transmit FIFO is empty
and the content of the transmit shift register (TSR) is also completely shifted.
▄
Receive FIFO threshold level interrupt: An interrupt will be generated when the FIFO received
data amount has reached the specified threshold level.

Register Map

The following table shows the USART registers and reset values.

Table 48. USART Register Map

Register
USRDR
USRCR
USRFCR
USRIER
USRSIFR
USRTPR
IrDACR
RS485CR
SYNCR
USRDLR
USRTSTR
Rev. 1.10
Offset
0x000 USART Data Register
0x004 USART Control Register
0x008 USART FIFO Control Register
0x00C USART Interrupt Enable Register
0x010 USART Status & Interrupt Flag Register
0x014 USART Timing Parameter Register
0x018 USART IrDA Control Register
0x01C USART RS485 Control Register
0x020 USART Synchronous Control Register
0x024 USART Divider Latch Register
0x028 USART Test Register
340 of 366
Description Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0180
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0010
0x0000_0000
November 09, 2018