32-Bit Arm
®
Cortex
®
-M3 MCU
HT32F12345
Timer Counter Register – CNTR
This register stores the timer counter value.
Offset:
0x080
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
RW
0 RW
7
Type/Reset
RW
0 RW
Bits
Field
[15:0]
CNTV
Timer Prescaler Register – PSCR
This register specifies the timer prescaler value to generate the counter clock.
Offset:
0x084
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
RW
0 RW
7
Type/Reset
RW
0 RW
Bits
Field
[15:0]
PSCV
Rev. 1.10
30
29
28
22
21
20
14
13
12
0 RW
0 RW
6
5
4
0 RW
0 RW
Descriptions
Counter Value
30
29
28
22
21
20
14
13
12
0 RW
0 RW
6
5
4
0 RW
0 RW
Descriptions
Prescaler Value
These bits are used to specify the prescaler value to generate the counter clock
frequency CK_CNT.
f
CK_PSC
, where the f
f
CK_CNT
PSCV[15
:
0]
1
277 of 590
27
26
Reserved
19
18
Reserved
11
10
CNTV
0 RW
0 RW
0 RW
3
2
CNTV
0 RW
0 RW
0 RW
27
26
Reserved
19
18
Reserved
11
10
PSCV
0 RW
0 RW
0 RW
3
2
PSCV
0 RW
0 RW
0 RW
is the prescaler clock source.
CK_PSC
25
24
17
16
9
8
0 RW
0
1
0
0 RW
0
25
24
17
16
9
8
0 RW
0
1
0
0 RW
0
November 28, 2018
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