IBM PowerPC 750GL Manuals

Manuals and User Guides for IBM PowerPC 750GL. We have 1 IBM PowerPC 750GL manual available for free PDF download: User Manual

IBM PowerPC 750GL User Manual

IBM PowerPC 750GL User Manual (377 pages)

RISC Microprocessor

Brand: IBM | Category: Computer Hardware | Size: 3.64 MB

Table of Contents

Table of Contents
3
List of Figures

13
List of Tables

15
About this Manual

19
1 Powerpc 750GX Overview

23
2 Programming Model

57
3 Instruction-Cache and Data-Cache Operation

121
4 Exceptions

151
5 Memory Management

179
- MMU Overview
  179
6 Instruction Timing

209
- Terminology and Conventions
  209
- Instruction Timing Overview
  211
- Figure 6-1. Pipelined Execution Unit
  212
- Figure 6-2. Superscalar/Pipeline Diagram
  212
- Figure 6-3. Powerpc 750GX Microprocessor Pipeline Stages
  214
- Table 6-1. Notation Conventions for Instruction Timing
  214
- Timing Considerations
  215
  - General Instruction Flow
    215
  - Instruction Fetch Timing
    216
    
    Cache Arbitration
    217
    
    Cache Hit
    217
    
    Figure 6-4. Instruction Flow Diagram
    218
    
    Figure 6-5. Instruction Timing-Cache Hit
    220
    
    Cache Miss
    222
    
    Figure 6-6. Instruction Timing-Cache Miss
    223
    
    Instruction Dispatch and Completion Considerations
    224
    
    L2 Cache Access Timing Considerations
    224
    
    Rename Register Operation
    224
    
    Instruction Serialization
    225
  - Execution-Unit Timings
    225
    
    Branch Processing Unit Execution Timing
    225
    
    Branch Folding
    226
    
    Branch Instructions and Completion
    227
    
    Figure 6-7. Branch Taken
    227
    
    Figure 6-8. Removal of Fall-Through Branch Instruction
    227
    
    Branch Prediction and Resolution
    228
    
    Figure 6-9. Branch Completion
    228
    
    Figure 6-10. Branch Instruction Timing
    231
    
    Effect of Floating-Point Exceptions on Performance
    232
    
    Floating-Point Unit Execution Timing
    232
    
    Integer Unit Execution Timing
    232
    
    Effect of Operand Placement on Performance
    233
    
    Load/Store Unit Execution Timing
    233
    
    Table 6-2. Performance Effects of Memory Operand Placement
    233
    
    Integer Store Gathering
    234
    
    System Register Unit Execution Timing
    234
  - Memory Performance Considerations
    235
    
    Caching and Memory Coherency
    235
    
    Effect of TLB Miss
    236
  - Instruction Scheduling Guidelines
    236
    
    Table 6-3. TLB Miss Latencies
    236
    
    Branch, Dispatch, and Completion-Unit Resource Requirements
    237
    
    Branch-Resolution Resource Requirements
    237
    
    Completion-Unit Resource Requirements
    237
    
    Dispatch-Unit Resource Requirements
    237
- Instruction Latency Summary
  238
- Table 6-4. Branch Instructions
  238
- Table 6-5. System-Register Instructions
  238
- Table 6-6. Condition Register Logical Instructions
  240
- Table 6-7. Integer Instructions
  240
- Table 6-8. Floating-Point Instructions
  242
- Table 6-9. Load-And-Store Instructions
  244
7 Signal Descriptions

249
- Signal Configuration
  250
- Figure 7-1. 750GX Signal Groups
  250
- Signal Descriptions
  251
  - Address-Bus Arbitration Signals
    251
    
    Bus Request (BR)-Output
    251
    
    Address Bus Busy (ABB)
    252
    
    Bus Grant (BG)-Input
    252
  - Address Transfer Start Signals
    253
    
    Transfer Start (TS)
    253
  - Address Transfer Signals
    254
    
    Address Bus (A[0-31])
    254
    
    Address-Bus Parity (AP[0-3])
    255
  - Address Transfer Attribute Signals
    255
    
    Table 7-1. Transfer Type Encodings for Powerpc 750GX Bus Master
    256
    
    Transfer Type (TT[0-4])
    256
    
    Table 7-2. Powerpc 750GX Snoop Hit Response
    257
    
    Transfer Size (TSIZ[0-2])-Output
    258
    
    Table 7-3. Data-Transfer Size
    259
    
    Transfer Burst (TBST)
    259
    
    Cache Inhibit (CI)-Output
    260
    
    Write-Through (WT)-Output
    260
    
    Global (GBL)
    261
  - Address Transfer Termination Signals
    262
    
    Address Acknowledge (AACK)-Input
    262
    
    Address Retry (ARTRY)
    263
  - Data-Bus Arbitration Signals
    264
    
    Data-Bus Grant (DBG)-Input
    264
    
    Data Bus Busy (DBB)
    265
    
    Data-Bus Write-Only (DBWO)
    265
  - Data-Transfer Signals
    266
    
    Data Bus (DH[0-31], DL[0-31])
    266
    
    Table 7-4. Data-Bus Lane Assignments
    266
    
    Data-Bus Parity (DP[0-7])
    267
    
    Table 7-5. DP[0-7] Signal Assignments
    267
    
    Data Bus Disable (DBDIS)-Input
    268
  - Data-Transfer Termination Signals
    268
    
    Transfer Acknowledge (TA)-Input
    268
    
    Data Retry (DRTRY)-Input
    269
    
    Table 7-6. Summary of Mode Select Signals
    269
    
    Transfer Error Acknowledge (TEA)-Input
    269
  - System Status Signals
    270
    
    Interrupt (INT)- Input
    270
    
    System Management Interrupt (SMI)-Input
    270
    
    Checkstop Input (CKSTP_IN)-Input
    271
    
    Checkstop Output (CKSTP_OUT)-Output
    271
    
    Machine-Check Interrupt (MCP)-Input
    271
  - Reset Signals
    272
    
    Hard Reset (HRESET)-Input
    272
    
    Soft Reset (SRESET)-Input
    272
  - Processor Status Signals
    273
    
    Quiescent Acknowledge (QACK)-Input
    273
    
    Quiescent Request (QREQ)-Output
    273
    
    Reservation (RSRV)-Output
    273
    
    Processor Mode Selection Signals
    274
    
    Time Base Enable (TBEN)-Input
    274
    
    TLB Invalidate Synchronize (TLBISYNC)-Input
    274
    
    I/O Voltage Select Signals
    275
    
    IEEE 1149.1A-1993 Interface Description
    275
    
    Lssd_Mode
    275
    
    Table 7-7. Bus Voltage Selection Settings
    275
    
    Table 7-8. IEEE Interface Pin Descriptions
    275
    
    Test Interface Signals
    275
    
    Bvsel
    276
    
    Clock Signals
    276
    
    L1_Tstclk
    276
    
    L2_Tstclk
    276
    
    Clock out (CLK_OUT)-Output
    277
    
    PLL Configuration (PLL_CFG[0:4])-Input
    277
    
    System Clock (SYSCLK)-Input
    277
    
    PLL Range (PLL_RNG[0:1])-Input
    278
    
    Power and Ground Signals
    278
8 Bus Interface Operation

279
9 L2 Cache

323
- L2 Cache Overview
  323
- L2 Cache Operation
  323
- Table 9-1. Interpretation of LRU Bits
  324
- Table 9-2. Modification of LRU Bits
  325
- Table 9-3. Effect of Locked Ways on LRU Interpretation
  325
- Figure 9-1. L2 Cache
  327
- L2 Cache Control Register (L2CR)
  329
- L2 Cache Initialization
  329
- L2 Cache Global Invalidation
  329
- L2 Cache Used as On-Chip Memory
  330
  - Locking the L2 Cache
    330
    
    Loading the Locked L2 Cache
    331
    
    Locked Cache Operation
    331
- Data-Only and Instruction-Only Modes
  332
- L2 Cache Test Features and Methods
  332
  - L2CR Support for L2 Cache Testing
    332
  - L2 Cache Testing
    333
- L2 Cache Timing
  333
10 Power and Thermal Management

335
- Dynamic Power Management
  335
- Programmable Power Modes
  335
  - Figure 10-1. 750GX Power States
    336
  - Table 10-1. 750GX Microprocessor Programmable Power Modes
    336
  - Power Management Modes
    337
    
    Doze Mode
    337
    
    Full on Mode
    337
    
    Nap Mode
    337
    
    Table 10-2. HID0 Power Saving Mode Bit Settings
    337
    
    Dynamic Power Reduction
    339
    
    Sleep Mode
    339
  - Power Management Software Considerations
    340
- 750GX Dual PLL Feature
  340
  - Overview
    340
  - Configuration Restriction on Frequency Transitions
    341
  - Dual PLL Implementation
    342
  - Figure 10-2. Dual PLL Block Diagram
    342
- Thermal Assist Unit
  343
- Instruction-Cache Throttling
  347
- Figure 10-5. Instruction Cache Throttling Control SPR Diagram
  347
- Table 10-4. ICTC Bit Field Settings
  348
11 Performance Monitor and System Related Features

349
- Performance-Monitor Interrupt
  349
- Special-Purpose Registers Used by Performance Monitor
  350
  - Table 11-1. Performance Monitor Sprs
    350
  - Performance-Monitor Registers
    351
    
    Monitor Mode Control Register 0 (MMCR0)
    351
    
    Monitor Mode Control Register 1 (MMCR1)
    351
    
    Performance-Monitor Counter Registers (Pmcn)
    351
    
    User Monitor Mode Control Register 0 (UMMCR0)
    351
    
    User Monitor Mode Control Register 1 (UMMCR1)
    351
    
    Table 11-2. PMC1 Events-MMCR0[19:25] Select Encodings
    352
    
    Table 11-3. PMC2 Events-MMCR0[26:31] Select Encodings
    352
    
    Table 11-4. PMC3 Events-MMCR1[0:4] Select Encodings
    353
    
    Table 11-5. PMC4 Events-MMCR1[5:9] Select Encodings
    354
    
    User Performance-Monitor Counter Registers (UPMC1-UPMC4)
    354
    
    Sampled Instruction Address Register (SIA)
    355
    
    User Sampled Instruction Address Register (USIA)
    355
  - Event Counting
    355
  - Event Selection
    356
  - Notes
    356
  - Debug Support
    357
    
    Data-Address Breakpoint
    357
    
    Overview
    357
  - JTAG/COP Functions
    357
    
    Introduction
    357
    
    Processor Resources Available through JTAG/COP Serial Interface
    357
    
    Figure 11-1. 750GX IEEE 1149.1A-1993/COP Organization
    358
  - Resets
    359
    
    Hard Reset
    359
    
    Soft Reset
    359
    
    Figure 11-2. Reset Sequence
    360
    
    Reset Sequence
    360
  - Checkstops
    361
    
    Checkstop Control Bits
    361
    
    Checkstop Sources
    361
    
    Table 11-6. HID0 Checkstop Control Bits
    361
    
    Open-Collector-Driver States During Checkstop
    362
    
    Vacancy Slot Application
    362
  - 750GX Parity
    363
    
    Enabling Parity Error Detection
    364
    
    Parity Control and Status
    364
    
    Parity Errors
    364
- Acronyms and Abbreviations
  
  365
- Index
  
  369
- Revision Log
  
  377

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