Powerpc 750Gx-Initiated Load/Store Operations; Performed Loads And Stores; Sequential Consistency Of Memory Accesses; Atomic Memory References - IBM PowerPC 750GX User Manual

User's Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor

3.3.5 PowerPC 750GX-Initiated Load/Store Operations

Load-and-store operations are assumed to be weakly ordered on the 750GX. The load/store unit (LSU) can
perform load operations that occur later in the program ahead of store operations, even when the data cache
is disabled (see Section 3.3.5.2). However, strongly ordered load-and-store operations can be enforced by
setting the invalid (I) bit (of the page WIMG bits) when address translation is enabled. Note that when address
translation is disabled (real-addressing mode), the default WIMG bits cause the I bit to be cleared (accesses
are assumed to be cacheable), and thus the accesses are weakly ordered. See Section 5.2 on page 195 for
a description of the WIMG bits when address translation is disabled.
The 750GX does not provide support for direct-store segments. Operations attempting to access a direct-
store segment will invoke a data-storage interrupt (DSI) exception. For additional information about DSI
exceptions, see Section 4.5.3, DSI Exception (0x00300), on page 169.

3.3.5.1 Performed Loads and Stores

The PowerPC Architecture defines a performed load operation as one that has the addressed memory loca-
tion bound to the target register of the load instruction. The architecture defines a performed store operation
as one where the stored value is the value that any other processor will receive when executing a load oper-
ation (that is of course, until it is changed again). With respect to the 750GX, caching-enabled (WIMG = x0xx)
loads and caching-enabled, write-back (WIMG = 00xx) stores are performed when they have arbitrated to
address the cache block. Note that in the event of a cache miss, these storage operations might place a
memory request into the processor's memory queue, but such operations are considered an extension to the
state of the cache with respect to snooping bus operations. Caching-inhibited (WIMG = x1xx) loads, caching-
inhibited (WIMG = x1xx) stores, and write-through (WIMG = 1xxx) stores are performed when they have been
successfully presented to the external 60x bus.

3.3.5.2 Sequential Consistency of Memory Accesses

The PowerPC Architecture requires that all memory operations executed by a single processor be sequen-
tially consistent with respect to that processor. This means that all memory accesses appear to be executed
in program order with respect to exceptions and data dependencies.
The 750GX achieves sequential consistency by operating a single pipeline to the cache/MMU. All memory
accesses are presented to the MMU in exact program order. Therefore, exceptions are determined in order.
Loads are allowed to bypass stores once exception checking has been performed for the store, but data
dependency checking is handled in the load/store unit so that a load will not bypass a store with an address
match. Note that, although memory accesses that miss in the cache are forwarded to the memory queue for
future arbitration for the external bus, all potential synchronous exceptions have been resolved before the
cache. In addition, although subsequent memory accesses can address the cache, full coherency checking
between the cache and the memory queue is provided to avoid dependency conflicts.

3.3.5.3 Atomic Memory References

The PowerPC Architecture defines the Load Word and Reserve Indexed (lwarx) and the Store Word Condi-
tional Indexed (stwcx.) instructions to provide an atomic update function for a single, aligned word of
memory. These instructions can be used to develop a rich set of multiprocessor synchronization primitives.
Note: Atomic memory references constructed using lwarx and stwcx. instructions depend on the presence
of a coherent memory system for correct operation. These instructions should not be expected to provide
Instruction-Cache and Data-Cache Operation gx_03.fm.(1.2)
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