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2.10.2.4 Transfer Byte Count (TBC) Field
The TBC field is used by the string indexed integer storage access instructions (lswx and stswx) as a byte
count. The TBC field is also written by mtspr(XER) with the value in (RS)
XER[TBC] is read (along with the rest of the XER) into a GPR by mfspr(XER).
2.11 Processor Control
Except for the MSR, each of the following registers is described in more detail in the following sections. The
MSR is described in more detail in Machine State Register (MSR) on page 301.
• Machine State Register (MSR) - Controls interrupts and other processor functions.
• Special Purpose Registers General (SPRGs) - SPRs for general purpose software use.
• Vector Save Register (VRSAVE) - Can be used to indicate which VRs are currently in use by a program.
• Processor Version Register (PVR) - Indicates the specific implementation of a processor.
• Thread Identification Register (TIR) - Indicates the specific instance of a thread within in a processor.
• Processor Identification Register (PIR) - Indicates the specific instance of a processor in a multiprocessor
system.
• Guest Processor Identification Register (GPIR) - Indicates the specific instance of a processor in a multi-
processor system for the guest state.
• Thread Enable Register (TENS, TENC) - Controls the thread run state.
• Thread Enable Status Register (TENSR) - Indicates the thread run state.
• External Process ID Registers (EPLC, EPSC) - Alternate PID for loads, stores, and cache operations.
• Core Configuration Register 0 (CCR0) - Controls specific processor functions, such as run controls.
• Core Configuration Register 1 (CCR1) - Controls specific processor functions, such as thread wakeup
controls.
• Core Configuration Register 2 (CCR2) - Controls various other processor functions.
• Instruction Unit Configuration Register 0 (IUCR0) - Contains various configuration options for the instruc-
tion unit.
• Instruction Unit Configuration Register 1(IUCR1) - Contains various configuration options for the instruc-
tion unit.
• Execution Unit Configuration Register 0 (XUCR0) - Contains various configuration options for the execu-
tion unit.
• Execution Unit Configuration Register 1(XUCR1) - Contains various configuration options for the execu-
tion unit.
• Execution Unit Configuration Register 2(XUCR2) - Contains various configuration options for the execu-
tion unit.
• Program Priority Register (PPR32) - Controls thread priority.
Version 1.3
October 23, 2012
User's Manual
A2 Processor
.
25:31
CPU Programming Model
Page 113 of 864
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