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15.3.5 Logical Address to Memory Address Mapping
SDRAM memory requires that addresses be divided into row and column portions. The relationship
between a logical address and the SDRAM row and column address is determined by the address
mode programmed in SDRAMO_BnCR[AM] and is shown in Table 15-6.
Table 15-6. Logical Address Bit on BA 1 :0 and MemAddr12:0 Versus Addressing Mode.
Bank Size
Address
BA
MemAddr
Mode
Organization
1
Phase
1
0
12 11
10
9
8
7
6
5
4
1
8MB
Row
7
9
7
9
10 11 12 13 14 15 16
11 x9x2
Column
7
9
7
9 AP 8
21 22 23 24 25
16 MB
Row
7
9
7
9
10 11 12 13 14 15 16
11x10x2
Column
7
9
7
9 AP
8
21 22 23 24 25
2
32MB
Row
7
8
7
9
10 11 12 13 14 15 16
12 x 9 x 4
Column
7
8
7
4
AP
6
21 22 23 24 25
64MB
Row
7
8
7
9
10 11 12 13 14 15 16
12x10x4
Column
7
8
7
4
AP
6
21 22 23 24 25
3
64MB
Row
6
7
8
9
10 11 12 13 14 15 16
13 x 9 x 4
Column
6
7
7
4
AP
5
21 22 23 24 25
128 MB
Row
6
7
8
9
10 11 12 13 14 15 16
13x10x4
Column
6
7
7
4 AP
5
21 22 23 24 25
256MB
Row
6
7
8
9
10 11 12 13 14 15 16
13x11x4
Column
6
7
7
4
2
AP
5
21 22 23 24 25
4
8/16 MB
Row
8
21
8
9
10 11 12 13 14 15 16
12 x 8 x 2/4
Column
8
21
8
4
AP
6
21 22 23 24 25
5
4/8 MB
Row
9
21
9
21 10 11 12 13 14 15 16
11 x 8 x 2/4
Column
9
21
9
21
AP
8
21
22 23 24 25
6
16/32 MB
Row
7
21
8
9
10 11 12 13 14 15 16
13 x 8 x 2/4
Column
7
21
8
9 AP
8
21 22 23 24 25
7
32 MB
Row
7
7
8
9
10 11 12 13 14 15 16
13 x 9 x 2
Column
7
7
7
4
AP 6
21 22 23 24 25
64MB
Row
7
7
8
9
10 11 12 13 14 15 16
13x10x2
Column
7
7
7
4
AP
6
21 22 23 24 25
Note 1: Memory organization is the number of rows x columns x internal banks.
Note 2: Column address bit 10 sent out on MemAddr11 for 13 x 11 x 4 parts.
3
2
1
0
17 18 19 20
26 27 28 29
17 18 19 20
26 27 28 29
17 18 19 20
26 27 28 29
17 18 19 20
26 27 28 29
17 18 19 20
26 27 28 29
17 18 19 20
26 27 28 29
17 18 19 20
26 27 28 29
17 18 19 20
26 27 28 29
17 18 19 20
26 27 28 29
17 18 19 20
26 27 28 29
17 18 19 20
26 27 28 29
17 18 19 20
26 27 28 29
Note 3: All read operations transfer 64-bits from SDRAM memory to the controller. Therefore,
MemAddrO is first driven with 0 and then 1. For data items narrower than 64-bits, the
requested byte(s) are fulfilled from the 64-bit doubleword.
15-8
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