Instruction Trace Record Formats And Ordering; Table 11-8. Core Instruction Trace Data And Control Signals; Table 11-9. First Instruction Trace Record Format - IBM A2 User Manual

Table 11-8. Core Instruction Trace Data and Control Signals

Trace Data Type
Instruction Opcode
xABCDE data pattern
Encoded Trace Record Type
First Instruction Trace Record Valid
Trace Record Valid
Instruction Effective Address (IEA)
MTSPR Data
Data Effective Address (DEA)
Data Real Address (DRA)

11.6.3 Instruction Trace Record Formats and Ordering

The first instruction trace record includes the opcode field, a unique data pattern, and other control signals
that enable the HTM and postprocessing software to identify it as the first trace record and determine what
additional trace records will follow. The number and type of additional trace records are determined by the
value of the encoded Trace Record Type field.
The tables in this section describe how the instruction trace records are driven onto the debug bus, and the
specific ordering of the trace records for each trace record type.

Table 11-9. First Instruction Trace Record Format

Debug Bus Bit
Number
0:31 Opcode.
32:35 Reserved.
36:55 Unique pattern for software identification (xABCDE).
56 First instruction trace record valid bit.
Version 1.3
October 23, 2012
Unit Size
Driving (Bits)
AXU, XU 32 32-bit opcode field.
AXU, XU 20 Specific data pattern. Part of the information used by software to identify
the first instruction trace record.
AXU, XU 2 A 2-bit encoded field included in the first instruction trace record, which
indicates how many data packets will follow. The trace record type
decode follows:
00 Opcode only.
01 Opcode and IEA.
10 Opcode and IEA and mtspr data.
11 Opcode and IEA, DEA, and DRA.
XU 2 There are two first record valid signals. One is driven on bit 56 of the
debug bus and is written to memory along with the other first instruction
trace record data. The other is driven on bit 64 and is used only by the
HTM.
XU 1 This signal is driven on bit 67 of the debug bus. It is used by the HTM to
determine when the corresponding bus data is a valid trace record.
XU 62 Because no address information is provided through the Ram registers,
any Rammed instructions executed in instruction trace mode has an asso-
ciated IEA of 0.
XU 64 Data written to an SPR from mtspr, mtmsr, and so forth
XU 64
XU 40 The DRA field is driven onto the debug bus noncontiguously by the LSU.
Correlation between the LSU address and debug bus is shown below:
debug_bus[08:12]  ex4_p_addr_q[53:57]
debug_bus[18:21]  ex4_p_addr_q[58:61]
debug_bus[33:43]  ex4_p_addr_q[22:32]
debug_bus[44:63]  ex4_p_addr_q[33:52]
(Sheet 1 of 2)
Comments
Function
Performance Events and Event Selection
User's Manual
A2 Processor
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