Self-Modifying Code; Instruction Cache Synonyms; Instruction Cache Control And Debug; Instruction Cache Management And Debug Instruction Summary - IBM A2 User Manual

User's Manual
A2 Processor
cache or within memory itself, by the A2 core through the execution of store instructions or by some other
mechanism in the system writing to memory, software must use cache management instructions to ensure
that the instruction cache is made coherent with these changes. This involves invalidating any obsolete
copies of these memory locations within the instruction cache so that they will be reread from memory the
next time they are referenced by program execution.

5.4.2.1 Self-Modifying Code

To illustrate the use of the cache management instructions to enforce instruction cache coherency, consider
the example of self-modifying code, whereby the program executing on the A2 core stores new data to
memory with the intention of later branching to and executing this new "data," which are actually instructions.
The following code example illustrates the required sequence for software to use when writing self-modifying
code. This example assumes that addr1 references a cacheable memory page.
stw regN, addr1 # Store the data (an instruction) in regN to addr1 in the data cache.
dcbst addr1
msync
icbi addr1
msync addr1
isync
At this point, software can begin executing the instruction at addr1 and be guaranteed that the new instruction
will be recognized.

5.4.2.2 Instruction Cache Synonyms

A synonym is a cache line that is associated with the same real address as another cache line that is in the
cache array at the same time. Such synonyms can occur when different virtual addresses are mapped to the
same real address, and the virtual address is used either as an index to the cache array (a virtually-indexed
cache) or as the cache line tag (a virtually-tagged cache).
The instruction cache on the A2 core is real-indexed and real-tagged. It is not possible for synonyms to exist
in the cache.

5.4.3 Instruction Cache Control and Debug

The A2 core provides various registers and instructions to control instruction cache operation and to help
debug instruction cache problems.

5.4.3.1 Instruction Cache Management and Debug Instruction Summary

In the instruction descriptions, the term "block" describes the unit of storage operated on by the cache block
instructions. For the A2 core, this is the same as a cache line.
The following instructions are used by software to manage the instruction cache.
Instruction and Data Caches
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# Write the new instruction from the data cache to memory.
# Wait until the data actually reaches the memory.
# Invalidate addr1 in the instruction cache if it exists.
# Wait for the instruction cache invalidation to take effect.
# Flush any prefetched instructions within the ICC and instruction
# unit and refetch them (an older copy of the instruction at addr1
# might have already been fetched).
Version 1.3
October 23, 2012