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20:05 Instruction Processing Function
General Description
The instruction processing function contains all the elements necessary to decode
and execute the instructions in the instruction set for 4381 Processors.
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instructions are partially processed by the instruction processing function and
partially processed by channel hardware. Extensive parity checking is done within
the instruction processing function to ensure data validity.
All instruction execution functions and most channel operations are microcode
controlled. Microinstructions are four bytes in length. Reloadable control storage
for the residence of instruction processing function microcode is standard.
Certain basic control and service functions are provided for 4381 Processors by the
support processor, a component of the support processor subsystem, instead of by
the instruction processing function. The support processor is a microcoded
controller with its own control storage. The support processor also handles
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operations for the operator console device and up to three other display consoles
and/or printer devices that are directly attached to a 4381 Processor. In addition,
the support processor controls diagnostic facilities (see discussions in Sections
20:15 and 60:15).
The instruction processing function in a 4381 Processor Model Group 11, 12, 1, or
2 has a 68-nanosecond cycle time. A 4381 Processor Model Group 13 has a 56-
nanosecond cycle time. The primary data path within the instruction processing
function and between the instruction processing function and processor storage and
the channels is eight bytes wide (as in 4341 Processors), which is the widest
primary data path implemented in IBM large-scale (System/370 and 30XX)
processors.
Elements included in the instruction processing function to perform instruction
execution are instruction buffers for instruction prefetching, an eight-byte-wide
arithmetic logic unit, an eight-byte MQ register, an eight-byte-wide byte shifter, an
eight-byte-wide bit shifter, and external registers. These same elements are
implemented in 4341 Processors and are functionally alike in 4381 and 4341
Processors.
The instruction processing function in 4381 Processors includes facilities like those
in 4341 Processors that are designed to speed up instruction execution. First,
during sequential instruction processing, instruction fetching is overlapped with
instruction execution. Unoverlapped instruction fetching usually occurs only when
a successful branch instruction is processed.
Second, several functions are performed during the single instruction cycle of 68 or
56 nanoseconds that precedes the execution cycle(s) of each instruction. The
following are performed during the instruction cycle of a 4381 Processor:
instruction decoding, selection of the microcode required to execute the instruction,
calculation of the required storage address using base register and displacement
values for instructions that reference storage, fetching of the contents of the
register 1 specification in RR- and RS-type instructions, testing for any
interruptions, and complete execution of certain instructions (BC and BCR when a
28
A Guide to the
IBM
4381 Processor
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