Exception Priorities; Exception Priorities For Integer Load, Store, And Cache Management Instructions - IBM PPC440X5 CPU Core User Manual

User's Manual
PPC440x5 CPU Core

6.7 Exception Priorities

PowerPC Book-E requires all synchronous (precise and imprecise) interrupts to be reported in program
order, as implied by the sequential execution model. The one exception to this rule is the case of multiple
synchronous imprecise interrupts. Upon a synchronizing event, all previously executed instructions are
required to report any synchronous imprecise interrupt-generating exceptions, and the interrupt(s) will then
be generated according to the general interrupt ordering rules outlined in Interrupt Order on page 201. For
example, if a mtmsr instruction causes MSR[FE0,FE1,DE] to all be set, it is possible that a previous Floating-
Point Enabled exception and a previous Debug exception both are still being presented (in the FPSCR and
DBSR, respectively). In such a scenario, a Floating-Point Enabled exception type Program interrupt will occur
first, followed immediately by a Debug interrupt.
For any single instruction attempting to cause multiple exceptions for which the corresponding synchronous
interrupt types are enabled, this section defines the priority order by which the instruction will be permitted to
cause a single enabled exception, thus generating a particular synchronous interrupt. Note that it is this
exception priority mechanism, along with the requirement that synchronous interrupts be generated in
program order, that guarantees that at any given time there exists for consideration only one of the synchro-
nous interrupt types listed in item 1 of Interrupt Order on page 201. The exception priority mechanism also
prevents certain debug exceptions from existing in combination with certain other synchronous interrupt-
generating exceptions.
This section does not define the permitted setting of multiple exceptions for which the corresponding interrupt
types are disabled. The generation of exceptions for which the corresponding interrupt types are disabled will
have no effect on the generation of other exceptions for which the corresponding interrupt types are enabled.
Conversely, if a particular exception for which the corresponding interrupt type is enabled is shown in the
following sections to be of a higher priority than another exception, the occurrence of that enabled higher
priority exception will prevent the setting of the other exception, independent of whether that other exception's
corresponding interrupt type is enabled or disabled.
Except as specifically noted below, only one of the exception types listed for a given instruction type will be
permitted to be generated at any given time, assuming the corresponding interrupt type is enabled. The
priority of the exception types are listed in the following sections ranging from highest to lowest, within each
instruction type.
Finally, note that Machine Check exceptions are defined by the PowerPC architecture to be neither synchro-
nous nor asynchronous. As such, Machine Check exceptions are not considered in the remainder of this
section, which is specifically addressing the priority of synchronous interrupts.

6.7.1 Exception Priorities for Integer Load, Store, and Cache Management Instructions

The following list identifies the priority order of the exception types that may occur within the PPC440x5 core
as the result of the attempted execution of any integer load, store, or cache management instruction.
Included in this category is the former opcode for the icbt instruction, which is an allocated opcode still
supported by the PPC440x5 core.
1. Debug (IAC exception)
2. Instruction TLB Error (Instruction TLB Miss exception)
3. Instruction Storage (Execute Access Control exception)
4. Program (Illegal Instruction exception)
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intrupts.fm.
September 12, 2002