Asynchronous Burst Read - Samsung S3C2416 User Manual

STATIC MEMORY CONTROLLER S3C2416X RISC MICROPROCESSOR
3.2

ASYNCHRONOUS BURST READ

The SMC supports sequential access asynchronous burst reads to four or eight consecutive locations in 8 or 16-
bit memories, as set using the BurstLenRead bits of the Control Register SMBCRx. Burst mode is enabled by
setting the Burst Mode bits, BMRead or BMWrite, in the Control register. This feature supports burst mode
devices and increases the bandwidth by using a reduced access time (that you can configure) for the sequential
reads, WSTBRD, following the first read, WSTRD. The chip select and output enable lines are held during the
burst, and only the address changes between subsequent accesses. At the end of the burst the chip select and
output enable lines are deasserted together.
Asynchronous page mode read operation is supported. This is enabled by setting the BMRead bit and by setting
the burst length using BurstLenRead in the SMBCRx register. Sequential bursts of up to four or eight beats are
the only type of access supported for page mode operation.
Figure 5-6 shows an external memory burst read transfer with two initial wait states, and one sequential wait
state. The first read has four AHB wait states inserted, and all additional sequential transfers have only one AHB
wait state.
Asynchronous Burst READ
SMCLK
A
A+4 A+8 A+C
ADDR
DATA(IN)
D(A) D(A+4) D(A+8)
nCS
WSTRD=2
WSTBRD =1 WSTBRD =1 WWSTBRD =1
Figure 5-6. External Burst ROM with WSTRD=2 and WSTBRD=1 Fixed Length Burst Read
5-6