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CONTROL REGISTERS
SYM
— System Mode Register
Bit Identifier
RESET Value
Read/Write
Addressing Mode
.7
.6–.5
.4–.2
.1
.0
NOTES:
1.
Because an external interface is not implemented for the S3C80A5B, SYM.7 must always be "0".
2.
You can select only one interrupt level at a time for fast interrupt processing.
3.
Setting SYM.1 to "1" enables fast interrupt processing for the interrupt level currently selected by SYM.2–SYM.4.
4.
Following a reset, you must enable global interrupt processing by executing an EI instruction (not by writing a "1"
to SYM.0).
4-26
.7
.6
0
–
R/W
–
Register addressing mode only
Tri-State External Interface Control Bit
0
Normal operation (disable tri-state operation)
1
Set external interface lines to high impedance (enable tri-state operation)
Not used for S3C80A5B.
Fast Interrupt Level Selection Bits
0
0
0
IRQ0
0
0
1
IRQ1
0
1
0
Not used for
0
1
1
S3C80A5B.
1
0
0
1
0
1
1
1
0
IRQ6
1
1
1
IRQ7
Fast Interrupt Enable Bit
0
Disable fast interrupt processing
1
Enable fast interrupt processing
Global Interrupt Enable Bit
0
Disable global interrupt processing
1
Enable global interrupt processing
.5
.4
.3
–
x
x
–
R/W
R/W
(1)
(2)
(3)
(4)
S3C80A5B
DEH
.2
.1
x
0
R/W
R/W
R/W
Set 1
.0
0
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