Features - Samsung S3C2501X User Manual

PRODUCT OVERVIEW

1.2 FEATURES

ARM940T Core processor
•
Fully 16/32-bit RISC architecture.
•
Harvard cache architecture with separate 4KB
Instruction and Data cache
•
Protection unit to partition memory and set
individual protection attributes for each partition
•
AMBA Bus architecture
•
Up to 166MHz operating frequency
Memory Controller
•
24-bit External Address Pins
•
2 Banks for SDRAM with 16/32 bit external bus.
•
8 Banks for Flash/ROM/SRAM/External I/O with
8/16/32-bit external bus.
•
One External Bus Master with Bus
Request/Acknowledge Pins
Ethernet Controllers
•
Buffered DMA (BDMA) engine using burst mode
•
BDMA Tx/Rx buffers (256-byte/256-byte)
•
MAC Tx/Rx FIFOs (80-byte/16-byte) to support
re-transmit after collision without DMA request
•
Data alignment logic
•
Support for old and new media (compatible with
existing 10M-bit/s networks)
•
10/100 Mbps operation to increase
price/performance options and to support
phased conversions
•
Full IEEE 802.3 compatibility for existing
applications
•
Media Independent interface (MII) or 7-wire
interface
•
Station management (STA) signaling for
external physical layer configuration and link
negotiation
1-2
On-chip CAM (21 addresses)
•
Full-duplex mode for doubled bandwidth
•
Pause operation hardware support for full-
duplex flow control
•
Long packet mode for specialized environments
•
Short packet mode for fast testing
•
PAD generation for ease of processing and
reduced processing time
Universal Asynchronous Receiver Transmitter
(UART)
•
Programmable baud rates
•
32-byte Transmit FIFO and 32-byte Receive
FIFO
•
UART source clock selectable (Internal clock
:PCLK2, External clock: EXT_CLK)
•
Auto baud rate detection
•
Infra-red (IR) transmit/receive
•
Insertion of one or two Stop bits per frame
•
Selectable 5-bit, 6-bit, 7-bit, or 8-bit data
transfers
•
Parity checking
DES/3DES Accelerator
•
DES or Triple DES mode
•
ECB or CBC mode
•
Encryption or decryption support
•
General DMA support
S3C2501X