Hitachi SH7751 Hardware Manual page 17

19.4.1 Interrupt Operation Sequence............................................................................... 747
19.4.2 Multiple Interrupts................................................................................................ 749
19.4.3 Interrupt Masking with MAI Bit .......................................................................... 749
19.5 Interrupt Response Time ................................................................................................... 750
Section 20 User Break Controller (UBC)
20.1 Overview ........................................................................................................................... 751
20.1.1 Features ................................................................................................................ 751
20.1.2 Block Diagram ..................................................................................................... 752
20.2 Register Descriptions......................................................................................................... 754
20.2.1 Access to UBC Registers ..................................................................................... 754
20.2.2 Break Address Register A (BARA) ..................................................................... 755
20.2.3 Break ASID Register A (BASRA) ....................................................................... 756
20.2.4 Break Address Mask Register A (BAMRA) ........................................................ 756
20.2.5 Break Bus Cycle Register A (BBRA) .................................................................. 757
20.2.6 Break Address Register B (BARB) ...................................................................... 759
20.2.7 Break ASID Register B (BASRB) ....................................................................... 759
20.2.8 Break Address Mask Register B (BAMRB)......................................................... 759
20.2.9 Break Data Register B (BDRB) ........................................................................... 759
20.2.10 Break Data Mask Register B (BDMRB) .............................................................. 760
20.2.11 Break Bus Cycle Register B (BBRB)................................................................... 761
20.2.12 Break Control Register (BRCR)........................................................................... 761
20.3 Operation........................................................................................................................... 763
20.3.1 Explanation of Terms Relating to Accesses ......................................................... 763
20.3.2 Explanation of Terms Relating to Instruction Intervals ....................................... 764
20.3.3 User Break Operation Sequence........................................................................... 765
20.3.4 Instruction Access Cycle Break............................................................................ 766
20.3.5 Operand Access Cycle Break ............................................................................... 767
20.3.6 Condition Match Flag Setting .............................................................................. 768
20.3.7 Program Counter (PC) Value Saved..................................................................... 768
20.3.8 Contiguous A and B Settings for Sequential Conditions...................................... 769
20.3.9 Usage Notes.......................................................................................................... 770
20.4 User Break Debug Support Function................................................................................. 771
20.5 Examples of Use................................................................................................................ 773
20.6 User Break Controller Stop Function ................................................................................ 775
20.6.1 Transition to User Break Controller Stopped State .............................................. 775
20.6.2 Cancelling the User Break Controller Stopped State ........................................... 775
20.6.3 Examples of Stopping and Restarting the User Break Controller ........................ 776
Section 21 Hitachi User Debug Interface (H-UDI)
21.1 Overview ........................................................................................................................... 777
21.1.1 Features ................................................................................................................ 777
21.1.2 Block Diagram ..................................................................................................... 777
Rev. 3.0, 04/02, page xvi of xxxviii
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