Motorola MPC823e Reference Manual page 1102

20.5.1 Freeze Indication (FRZ)
The internal freeze signal is connected to all relevant internal modules that can be
programmed to stop all operations in response to freeze signal assertion. To enable a
software monitor debugger to signal that the debug software is now executed, the internal
freeze signal can be asserted or negated when debug mode is disabled.
Assertion of the freeze signal is broadcasted to the external world over FRZ. Asserting and
negating the freeze signal when in disabled debug mode is controlled by the ICR and DER,
as illustrated in Figure 20-6.
To assert the FRZ signal, the software must be programmed to use the relevant bits in the
DER. To negate the FRZ signal, the software must read the ICR to clear it and perform an
rfi instruction. If the ICR is not cleared before the rfi instruction is performed, the FRZ signal
is not negated. Therefore, nested exception tracing can be supported by the software
monitor debugger without affecting the value of the FRZ signal. Only before the last rfi
instruction does the software need to clear the ICR. This process enables the software to
accurately control FRZ assertion or negation.
20.6 PROGRAMMING THE DEVELOPMENT PORT REGISTERS
Normally, the development port registers reside in the control register space and can be
accessed using the mtspr and mfspr instructions. They also reside in the memory map I/O
to be accessed by the ld and st instructions. The addresses of these registers are in
Table 6-9 of Section 6 Development Capabilities and Interface.
20.6.1 Protecting the Development Port Registers
The development support registers are protected as shown in the following table. Take note
of the ICR and DPDR registers' special behavior.
Table 20-12. Development Support Register Protection
OPERATION MSR
PR
Read Register 0
0
0
1
Write Register 0
0
0
1
MOTOROLA
DEBUG IN DEBUG
MODE MODE
ENABLE
0 X A read is performed and when reading ICR, it is also
cleared.
1 0 A read is performed and when reading ICR, it is not
cleared.
1 1 A read is performed and when reading ICR, it is also
cleared.
X X A read is not performed, a program interrupt is
generated, and when reading ICR, it is not cleared.
0 X A write is performed, a write to ICR is ignored, and a
write to DPDR is ignored.
1 0 A write is ignored.
1 1 A write is performed and a write to ICR is ignored.
X X A write is not performed, but a program interrupt is
generated.
MPC823e REFERENCE MANUAL
Development Capabilities and Interface
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