Pin Control Register (Pcr); Pin Control Register (Pcr) Field Descriptions - Texas Instruments TMS320C6201 Reference Manual

Figure 11–3.Pin Control Register (PCR)
31
15 14 13 12 11
Rsvd XIOEN RIOEN FSXM
R,+0 RW,+0 RW,+0 RW,+0
Table 11–6. Pin Control Register (PCR) Field Descriptions
Name Function
Receiver in general-purpose I/O mode only when RRST = 0 in SPCR
RIOEN
RIOEN = 0: DR and CLKS pins are not general-purpose inputs. FSR and CLKR are
RIOEN = 1: DR and CLKS pins are general-purpose inputs. FSR and CLKR are general-
Transmitter in general-purpose I/O mode only when XRST = 0 in SPCR
XIOEN
XIOEN = 0: CLKS pin is not a general-purpose input. DX pin is not a general purpose
XIOEN = 1: CLKS pin is a general-purpose input. DX pin is a general-purpose output.
FSXM Transmit frame synchronization mode
FSXM = 0: Frame synchronization signal is provided by an external source. FSX is
FSXM = 1: Frame synchronization generation is determined by the sample rate gen-
FSRM Receive frame synchronization mode
FSRM = 0: Frame synchronization signals are generated by an external device.
FSRM = 1: Frame synchronization signals are generated internally by the sample rate
10 9 8 7
FSRM CLKXM CLKRM Rsvd
RW,+0 RW,+0 RW, +0 R,+0
not general-purpose I/Os and perform serial port operation.
purpose I/Os. These serial port pins do not perform serial port operation.
output. FSX and CLKX are not general-purpose I/Os.
FSX and CLKX are general-purpose I/Os. These serial port pins do not per-
form serial port operation.
an input pin.
erator frame synchronization mode bit FSGM in the SRGR.
FSR is an input pin.
generator. FSR is an output pin except when GSYNC = 1 (see section
11.5.1.1) in SRGR.
McBSP Interface Signals and Registers
reserved
R, +0
6 5
CLKS_STAT DX_STAT DR_STAT
RW,+0 RW,+0
Multichannel Buffered Serial Ports
4 3 2 1
FSXP FSRP CLKXP
R,+0 RW,+0 RW,+0 RW,+0
Section
11.8
11.8
11.5.3.3
and
11.8
11.5.3.2
and
11.8
16
0
CLKRP
RW,+0
11-11