Texas Instruments TMS320C6201 Reference Manual page 436

Designing Your Target System's Emulator Connector (14-Pin Header)
15.1 Designing Your Target System's Emulator Connector (14-Pin Header)
Figure 15–1. 14-Pin Header Signals and Header Dimensions
Table 15–1. 14-Pin Header Signal Descriptions
15-2
JTAG target devices support emulation through a dedicated emulation port.
This port is a superset of the IEEE 1149.1 standard and is accessed by the
emulator. To communicate with the emulator, your target system must have
a 14-pin header (two rows of seven pins) with the connections that are shown
in Figure 15–1. Table 15–1 describes the emulation signals.
TMS 1
TDI 3
PD (V ) 5
CC
TDO 7
TCK_RET 9
TCK 11
EMU0 13
† While the corresponding female position on the cable connector is plugged to prevent improper
connection, the cable lead for pin 6 is present in the cable and is grounded, as shown in the sche-
matics and wiring diagrams in this document.
Signal Description
TMS Test mode select
TDI Test data input
TDO Test data output
TCK Test clock. TCK is a 10.368-MHz clock
source from the emulation cable pod. This
signal can be used to drive the system test
clock
‡
TRST Test reset
EMU0 Emulation pin 0
EMU1 Emulation pin 1
PD(V ) Presence detect. Indicates that the emula-
CC
tion cable is connected and that the target is
powered up. PD should be tied to V
target system.
TCK_RET Test clock return. Test clock input to the
emulator. May be a buffered or unbuffered
version of TCK.
GND Ground
† I = input; O = output
‡ Do not use pullup resistors on TRST: it has an internal pulldown device. In a low-noise
environment, TRST can be left floating. In a high-noise environment, an additional pulldown
resistor may be needed. (The size of this resistor should be based on electrical current
considerations.)
2 TRST
4 GND
†
6 no pin (key)
8 GND
10 GND
12 GND
14 EMU1
Header Dimensions:
Pin-to-pin spacing, 0.100 in. (X,Y)
Pin width, 0.025-in. square post
Pin length, 0.235-in. nominal
†
Emulator
State
O
O
I
O
O
I
I
I
in the
CC
I
†
Target
State
I
I
O
I
I
I/O
I/O
O
O