Texas Instruments TMS320C6201 Reference Manual page 401

SPI Protocol: CLKSTP
Figure 11–54 is the timing diagram when CLKSTP = 10b. In this SPI transfer
format, the transition of the first clock edge (CLKX) marks the beginning of data
transfer, provided the slave enable (FSX/SS) is already asserted. Data trans-
fer is synchronized to the first clock edge. Figure 11–55 is the timing diagram
when CLKSTP = 11b. Data transfer begins before the transition of the serial
clock. Therefore, the transition of the slave enable signal FSX/SS from high
to low, instead of the transition of the serial clock, marks the beginning of trans-
fer in this SPI transfer format. The McBSP clock stop mode requires single-
phase frames ((R/X)PHASE = 0) and one element per frame ((R/X)FRLEN =
0).
When the McBSP is configured to operate in SPI mode, both the transmitter
and the receiver operate together as a master or a slave. The McBSP is a
master when it generates clocks. When the McBSP is the SPI master, CLKX
drives both its own internal receive clock CLKR and the serial clock SCK of the
SPI slave. In conjunction with CLKSTP enabled, CLKXM = 1 (in PCR)
indicates that the McBSP is a master, and CLKXM = 0 indicates that the
McBSP is an SPI slave. The slave enable signal (FSX/SS) enables the serial
data input and output driver on the slave device (the device not providing the
output clock).
Multichannel Buffered Serial Ports 11-83