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Multichannel Selection Operation
In the case when two McBSPs are used to transmit data over the same TDM
line, bus contention occurs if DXENA = 0. The first McBSP turns off the
transmission of the last data bit (changes DX from valid to Hi–Z) after a disable
time specified in the datasheet. As shown in Figure 11–51, this disable time
is measured from the CLKX active clock edge. The next McBSP turns on its
DX pin (changes from Hi–Z to valid) after a delay time. Again, this delay time
is measured from the CLKX active clock edge. Bus contention occurs because
the dead time between the two devices is not enough. You need to apply
alternative software or hardware methods to ensure proper multichannel
operation in this case.
If you set DXENA = 1 in the second McBSP, the second McBSP turns on its
DX pin after two CPU-clock cycles of extra delay time. This ensures that the
previous McBSP on the same DX line is disabled before the second McBSP
starts driving out data. The DX enabler controls only the high impedance en-
able on the DX pin, not the data itself. Data is shifted out to the DX pin at the
same time as in the case when DXENA = 0. The only difference is that with
DXENA = 1, the DX pin is masked to high impedance for two extra CPU cycles
before the data is seen on the TDM data line. Therefore only the first bit of data
is delayed.
Multichannel Buffered Serial Ports
11-79
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