Pin Control Register (Pcr); Pin Control Register (Pcr) Field Descriptions - Texas Instruments TMS320C6000 DSP Reference Manual

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11.12

Pin Control Register (PCR)

The serial port is configured via the serial port control register (SPCR) and the pin control register (PCR) .
The PCR is also used to configure the serial port pins as general-purpose inputs or outputs during
receiver and/or transmitter reset (for more information see section
status control bits. The PCR is shown in
31
15 14
Reserved
R-0
7 6
(1)
Reserved CLKSSTAT
R-0 R-0
LEGEND: R = Read only; R/W = Rear/Write; -n = value afer reset
(1)
If writing to this field, always write the default value of 0 to ensure proper McBSP operation.
Bit Field
31-14 Reserved
13 XIOEN
12 RIOEN
11 FSXM
10 FSRM
9 CLKXM
8 CLKRM
SPRU580E – December 2005
Figure 11-12
Figure 11-12. Pin Control Register (PCR)
Reserved
13 12
XIOEN RIOEN
R/W-0 R/W-0
5 4
DXSTAT SRSTAT
R/W-0 R-0
Table 11-18. Pin Control Register (PCR) Field Descriptions
Value Description
0 Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
Transmit general-purpose I/O mode only when transmitter is disabled (XRST = 0 in
SPCR).
0 DX, FSX, and CLKX pins are configured as serial port pins and do not function as
general-purpose I/O pins.
1 DX pin is configured as general-purpose output pin; FSX and CLKX pins are
configured as general-purpose I/O pins. These serial port pins do not perform serial
port operations.
Receive general-purpose I/O mode only when receiver is disabled (RRST = 0 in
SPCR).
0 DR, FSR, CLKR, and CLKS pins are configured as serial port pins and do not
function as general-purpose I/O pins.
1 DR and CLKS pins are configured as general-purpose input pins; FSR and CLKR
pins are configured as general-purpose I/O pins. These serial port pins do not
perform serial port operations.
Transmit frame-synchronization mode bit.
0 Frame-synchronization signal is derived from an external source.
1 Frame-synchronization signal is determined by FSGM bit in SRGR.
Receive frame-synchronization mode bit.
0 Frame-synchronization signal is derived from an external source. FSR is an input pin.
1 Frame-synchronization signal is generated internally by the sample-rate generator.
FSR is an output pin, except when GSYNC = 1 in SRGR.
Transmitter clock mode bit.
0 CLKX is an input pin and is driven by an external clock.
1 CLKX is an output pin and is driven by the internal sample-rate generator.
In SPI mode when CLKSTP in SPCR is a non-zero value:
0 MCBSP is a slave and clock (CLKX) is driven by the SPI master in the system.
CLKR is internally driven by CLKX.
1 MCBSP is a master and generates the clock (CLKX) to drive its receive clock
(CLKR) and the shift clock of the SPI-compliant slaves in the system.
Receiver clock mode bit.
Chapter
and described in Table
R-0
11 10
FSXM FSRM
R/W-0 R/W-0
3 2
FSXP FSRP
R/W-0 R/W-0

Pin Control Register (PCR)

10). The PCR contains McBSP
11-18.
9 8
CLKXM CLKRM
R/W-0 R/W-0
1 0
CLKXP CLKRP
R/W-0 R/W-0
Registers
16
101