Texas Instruments TMS320C6201 Reference Manual page 373

11.5.1.1 Sample Rate Generator Register (SRGR)
Figure 11–39. Sample Rate Generator Register (SRGR)
31 30
GSYNC CLKSP
RW, +0 RW, +0
15
Table 11–14. Sample Rate Generator Register (SRGR) Field Summary
Name Function
GSYNC Sample rate generator clock synchronization. Used only when the external clock
(CLKS) drives the sample rate generator clock (CLKSM = 0).
GSYNC = 0: The sample rate generator clock (CLKG) is free running.
GSYNC = 1: (CLKG) is running but is resynchronized, and the frame sync signal
CLKSP CLKS polarity clock edge select. Used only when the external clock CLKS drives
the sample rate generator clock (CLKSM = 0).
CLKSP = 0: The rising edge of CLKS generates CLKG and FSG.
CLKSP = 1: The falling edge of CLKS generates CLKG and FSG.
CLKSM McBSP sample rate generator clock mode
CLKSM = 0: The sample rate generator clock is derived from CLKS.
CLKSM = 1: (Default value) The sample rate generator clock is derived from the
internal clock source.
FSGM Sample rate generator transmit frame synchronization mode. Used when FSXM
= 1 in PCR.
FSGM = 0: The transmit frame sync signal (FSX) is generated on every DXR-to-
FSGM = 1: The transmit frame sync signal is driven by the sample rate generator
The sample rate generator register (SRGR) shown in Figure 11–39 and
summarized in Table 11–14, controls the operation of various features of
the sample rate generator. This section describes the fields in the SRGR.
29 28
FSGM
CLKSM
RW, +1 RW, +0
FWID
RW, +0
(FSG) is generated only after the receive frame synchronization sig-
nal (FSR) is detected. Also, the frame period (FPER) is a don't care
because the period is dictated by the external frame sync pulse.
XSR copy.
frame sync signal, FSG.
27
8 7
Multichannel Buffered Serial Ports
Programmable Clock and Framing
FPER
RW, +0
CLKGDV
RW, +1
16
0
Section
11.5.2.4
11.5.2.3
11.5.2.1
11.5.3.3
11-55