Tms320C6211/C6711 Sdram Three Word Write - Texas Instruments TMS320C6201 Reference Manual

SDRAM Interface
9.4.9.2 TMS320C6211
Figure 9–27. TMS320C6211/C6711 SDRAM Three Word Write
ECLKOUT
CEx
BE[3:0]
EA[21:13]
EA[11:2]
EA12
ED[31:0]
SDRAS
SDCAS
SDWE
9-40
/
C6711 SDRAM Write
All SDRAM writes have a burst length of four on the 'C6211/C6711. The bank is
activated with the row address during the ACTV command. There is no latency
on writes, so data is output on the same cycle as the column address. Writes to
particular bytes are disabled via the appropriate DQM inputs; this feature allows
for byte and halfword writes. Figure 9–27 shows the timing for a three-word write
on the 'C6211/C6711. Since the default 'C6211/C6711 write-burst length is four
words, the last write is masked out via the byte enable signals. On the
'C6211/C6711, idle cycles are inserted as controlled by the parameters of the
SDRAM extension register fields (WR2RD, WR2DEAC, WR2WR, TWR). The
bank is then deactivated with a DEAC command for 'C6211/C6711, and the
memory interface can begin a new page access. If no new access is pending,
the DEAC command is not performed until the page information becomes inval-
id (see section 9.4.2). The values on EA[15:13] during column accesses and
the DEAC command are the values latched during the ACTV command.
Write
BE1 BE2 BE3
Bank
Column
SDRAM SDRAM
latches latches
D1 D2
D1 D2
BE4
SDRAM D4
latches blocked by BEx high
D3
D3