Texas Instruments TMS320C6201 Reference Manual page 349

Data Transmission and Reception
Another common operation uses a data delay of 2. This configuration allows the
serial port to interface to different types of T1 framing devices in which the data
stream is preceded by a framing bit. During the reception of such a stream with
a data delay of two bits, the framing bit appears after a 1-bit delay and data ap-
pears after a 2-bit delay). The serial port essentially discards the framing bit from
the data stream, as shown in Figure 11–13. In transmission, by delaying the first
transfer bit, the serial port essentially inserts a blank period (a high-impedance
period) in place of the framing bit. Here, it is expected that the framing device in-
serts its own framing bit or that the framing bit is generated by another device.
Alternatively, you may pull up or pull down DX to achieve the desired value.
Figure 11–13. 2-Bit Data Delay Used to Discard Framing Bit
CLKR
FSR
2 Bit Periods
DR
Framing Bit B7 B6 B5
Multichannel Buffered Serial Ports 11-31