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11.5.2 Data Clock Generation
11.5.2.1 Input Clock Source Mode: CLKSM
11.5.2.2 Sample Rate Generator Data Bit Clock Rate: CLKGDV
When the receive/transmit clock mode is set to 1 (CLK(R/X)M = 1), the data
clocks (CLK(R/X)) are driven by the internal sample rate generator output
clock, CLKG. You can select for the receiver and transmitter from a variety of
data bit clocks including:
The input clock to the sample rate generator, which can be either the inter-
nal clock source or a dedicated external clock source (CLKS). The internal
clock source for the 'C6211/C6711 is CPU clock, while the internal clock
source for 'C6211/C6711 is CPU/2 clock (half of the CPU clock frequency).
The input clock source (internal clock source or external clock CLKS) to
the sample rate generator can be divided down by a programmable value
(CLKGDV) to drive CLKG.
Regardless of the source to the sample rate generator, the rising edge of
CLKSRG (see Figure 11–38) generates CLKG and FSG (see section
11.5.2.3).
The CLKSM bit in the SRGR selects either the CPU clock (CLKSM = 1) or the
external clock input (CLKSM = 0), CLKS, as the source for the sample rate
generator input clock. Any divide periods are divide-downs calculated by the
sample rate generator and are timed by this input clock selection. The McBSP
cannot run faster than half of the CPU clock frequency. Therefore, when
CLKSM = 1, the minimum value of CLKGDV should be 1 for the
'C6201/C6202/C6701. For the 'C6211/C6711, even if CLKSM = 1 you can set
CLKGDV to the minimum of 0 because a CPU/2 clock drives the sample rate
generator.
The first divider stage generates the serial data bit clock from the input clock.
This divider stage uses a counter that is preloaded by CLKGDV and that con-
tains the divide ratio value. The output of this stage is the data bit clock that
is output on the sample rate generator output, CLKG, and that serves as the
input for the second and third divider stages.
CLKG has a frequency equal to 1/(CLKGDV+1) of the sample rate generator
input clock. Thus, the sample-rate generator input clock frequency is divided
by a value between 1 and 256. When CLKGDV is odd or equal to 0, the CLKG
duty cycle is 50%. When CLKGDV is an even value (2p) the high state duration
is p + 1 cycles and the low state duration is p cycles.
Programmable Clock and Framing
Multichannel Buffered Serial Ports
11-57
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