Texas Instruments TMS320C6201 Reference Manual page 470

Index
memory map 2-3
boot configuration 10-5
memory mapped operation 3-4
memory mapped registers 9-9
memory request priority 9-61
memory type field (MTYPE) 8-9
memory
external interface 9-2
types and 'C6202 9-24
widths 9-14
memory–mapped registers 8-7
million instructions per second (MIPS) 1-4
mode
asynchronous 8-12
synchronous host port 8-26
modes
16–bit ROM 9-53
asynchronous host port 8-41
asynchronous I/O 8-3
cache 3-5
cache enabled 2-3
destination update mode (DUM) 6-31
FIFO output enable signal 8-14
freeze or bypass 4-6
host port (mutually exclusive) 8-5
host port interface 8-3
I/O port (non–exclusive) 8-5
internal program memory 2-3
level 1 data cache 4-10
mapped 3-4
power down 14-5
pulse and clock 12-10
slave 8-3
source update mode 6-30
synch FIFO 8-13
synchronous FIFO 8-3
monitoring , flag 8-19
MTYPE field 9-14
MTYPE, write hold, and read hold bit fields 9-13
multichannel buffered serial port (McBSP,
introduction 1-11
multichannel buffered serial port (McBSP) 1-9, 4-2,
8-4
channel enable diagram 11-72
channel enable register 11-76
CLKP bit 11-13
clock configuration 11-23
clocking examples 11-65
Index-12
companding data formats 11-51
companding DLB method 11-52
companding hardware 11-50
companding nonDLB method 11-52
configuration 11-7
control register 11-7
CPU interrupts 11-22
data delay 11-30
data packing 11-39
data reception 11-18
data transmission 11-18
double-rate clock 11-67
double-rate ST-BUS clock 11-65
element length 11-28
end-of-block interrupt 11-78
end-of-frame interrupt 11-78
exception conditions 11-41
features 11-2
frame configuration 11-23
frame frequency 11-35
frame generation 11-53
frame sync signal generation 11-61
frame synch ignore bits 11-39
interface signals 11-3
multi hannel enable 11-71
multichannel selection operation 11-68
multiphase frame example: AC97 11-32
overrun 11-41
pins as general-purpose I/O 11-87
programmable clock 11-53
RDATDLY 11-30
receive control register 11-14
frame synchronization 11-36
receive operation 11-34
registers 11-3
reset 11-18
RFULL 11-41
rsyncherr 11-43
sample rate generator 11-54
reset procedure 11-56
sample rate generator register (SRGR) 11-55
sample rate generator reset 11-20
single-rate ST-BUS clock 11-66
SPI protocol (CLKSTP) 11-80
standard operation 11-33
transmit control register 11-14
transmit data companding 11-51
transmit ready 11-22
transmit with data overwrite 11-45
unexpected frame sync pulse 11-37